{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,31]],"date-time":"2024-10-31T02:48:22Z","timestamp":1730342902644,"version":"3.28.0"},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.23919\/date.2019.8715123","type":"proceedings-article","created":{"date-parts":[[2019,5,16]],"date-time":"2019-05-16T17:29:07Z","timestamp":1558027747000},"page":"504-509","source":"Crossref","is-referenced-by-count":8,"title":["Realization of Four-Terminal Switching Lattices: Technology Development and Circuit Modeling"],"prefix":"10.23919","author":[{"given":"Serzat","family":"Safaltin","sequence":"first","affiliation":[]},{"given":"Oguz","family":"Gencer","sequence":"additional","affiliation":[]},{"given":"M. Ceylan","family":"Morgul","sequence":"additional","affiliation":[]},{"given":"Levent","family":"Aksoy","sequence":"additional","affiliation":[]},{"given":"Sebahattin","family":"Gurmen","sequence":"additional","affiliation":[]},{"given":"Csaba Andras","family":"Moritz","sequence":"additional","affiliation":[]},{"given":"Mustafa","family":"Altun","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1002\/adma.201602418"},{"key":"ref11","article-title":"A mapping methodology of boolean logic circuits on memristor crossbar","volume":"99","author":"xie","year":"2017","journal-title":"IEEE TCAD"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/INEC.2008.4585651"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2661632"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2016.94"},{"key":"ref15","first-page":"1214","article-title":"Manufacturing pathway and experimental demonstration for nanoscale fine-grained 3-d integrated circuit fabric","author":"rahman","year":"2015","journal-title":"NANO"},{"key":"ref4","article-title":"Optimal and heuristic algorithms to synthesize lattices of four-terminal switches","author":"morgul","year":"0","journal-title":"Integration"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.23919\/DATE.2019.8714809"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1126\/science.1066192"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/384285.379262"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3154-4"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/s00339-004-3149-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2018.05.004"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.08.004"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2011.170"}],"event":{"name":"2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)","start":{"date-parts":[[2019,3,25]]},"location":"Florence, Italy","end":{"date-parts":[[2019,3,29]]}},"container-title":["2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8704855\/8714721\/08715123.pdf?arnumber=8715123","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,3]],"date-time":"2019-06-03T19:50:22Z","timestamp":1559591422000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8715123\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.23919\/date.2019.8715123","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}