{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T22:03:39Z","timestamp":1777586619748,"version":"3.51.4"},"reference-count":28,"publisher":"Walter de Gruyter GmbH","issue":"2","license":[{"start":{"date-parts":[[2021,1,29]],"date-time":"2021-01-29T00:00:00Z","timestamp":1611878400000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,4,1]]},"abstract":"<jats:title>Abstract<\/jats:title>\n                  <jats:p>This paper presents FPGA and softcore CPU based solution for large datasets parallel core calculation using rough set methods. Architectures shown in this paper have been tested on two real datasets running presented solutions inside FPGA unit. Tested datasets had 1 000 to 10 000 000 objects. The same operations were performed in software implementation. Obtained results show the big acceleration in computation time using hardware supporting core generation in comparison to pure software implementation.<\/jats:p>","DOI":"10.2478\/jaiscr-2021-0007","type":"journal-article","created":{"date-parts":[[2021,4,6]],"date-time":"2021-04-06T13:50:45Z","timestamp":1617717045000},"page":"99-110","source":"Crossref","is-referenced-by-count":6,"title":["Hardware Rough Set Processor Parallel Architecture in FPGA for Finding Core in Big Datasets"],"prefix":"10.2478","volume":"11","author":[{"given":"Maciej","family":"Kopczy\u0144ski","sequence":"first","affiliation":[{"name":"Faculty of Computer Science , Bialystok University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomasz","family":"Grze\u015b","sequence":"additional","affiliation":[{"name":"Faculty of Computer Science , Bialystok University of Technology"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"374","published-online":{"date-parts":[[2021,1,29]]},"reference":[{"key":"2026042814174431321_j_jaiscr-2021-0007_ref_001_w2aab3b7b4b1b6b1ab1ab1Aa","doi-asserted-by":"crossref","unstructured":"[1] Borowik, G.; Jankowski, J.; Kowalski K. Fast algorithm for feature extraction. Proceedings of SPIE 9662, In Photonics Applications in Astronomy, Communications, Industry, and High-Energy Physics Experiments, Proceedings of SPIE 2015, pp. 1110\u20131117.10.1117\/12.2205909","DOI":"10.1117\/12.2205909"},{"key":"2026042814174431321_j_jaiscr-2021-0007_ref_002_w2aab3b7b4b1b6b1ab1ab2Aa","doi-asserted-by":"crossref","unstructured":"[2] Choroma\u0144ski, M.; Grze\u015b, T.; Ho\u0144ko, P. Two FPGA Devices in the Problem of Finding Minimal Reducts. In Lecture Notes in Computer Science, Publisher: Springer, 2019, Vol. 11703, pp. 410\u2013420.","DOI":"10.1007\/978-3-030-28957-7_34"},{"key":"2026042814174431321_j_jaiscr-2021-0007_ref_003_w2aab3b7b4b1b6b1ab1ab3Aa","doi-asserted-by":"crossref","unstructured":"[3] Czo\u0142ombitko, M.; Stepaniuk, J. Generating core based on discernibility measure and MapReduce. Proceedings of the Pattern recognition and machine intelligence: 6th International conference, PReMI 2015, Warsaw, Poland, June 30\u2013July 3, 2015, Lecture Notes in Computer Science, vol. 9124, pp. 367\u2013376.10.1007\/978-3-319-19941-2_35","DOI":"10.1007\/978-3-319-19941-2_35"},{"key":"2026042814174431321_j_jaiscr-2021-0007_ref_004_w2aab3b7b4b1b6b1ab1ab4Aa","doi-asserted-by":"crossref","unstructured":"[4] T. Geng et al., O3BNN-R: An Out-of-Order Architecture for High-Performance and Regularized BNN Inference, in IEEE Transactions on Parallel and Distributed Systems, vol. 32, no. 1, 1 Jan. 2021, doi: 10.1109\/TPDS.2020.3013637, pp. 199\u2013213.","DOI":"10.1109\/TPDS.2020.3013637"},{"key":"2026042814174431321_j_jaiscr-2021-0007_ref_005_w2aab3b7b4b1b6b1ab1ab5Aa","doi-asserted-by":"crossref","unstructured":"[5] Grze\u015b T., Kopczy\u0144ski M. Hardware Implementation on Field Programmable Gate Array of Two-Stage Algorithm for Rough Set Reduct Generation. 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