{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,6,29]],"date-time":"2024-06-29T13:25:50Z","timestamp":1719667550646},"reference-count":25,"publisher":"University of Zielona G\u00f3ra, Poland","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2007,3,1]]},"abstract":"<jats:title>FSM Encoding for BDD Representations<\/jats:title><jats:p>We address the problem of encoding the state variables of a finite state machine such that the BDD representing the next state function and the output function has the minimum number of nodes. We present an exact algorithm to solve this problem when only the present state variables are encoded. We provide results on MCNC benchmark circuits.<\/jats:p>","DOI":"10.2478\/v10006-007-0011-6","type":"journal-article","created":{"date-parts":[[2007,4,11]],"date-time":"2007-04-11T22:05:46Z","timestamp":1176329146000},"page":"113-124","source":"Crossref","is-referenced-by-count":6,"title":["FSM Encoding for BDD Representations"],"prefix":"10.61822","volume":"17","author":[{"given":"Wilsin","family":"Gosti","sequence":"first","affiliation":[]},{"given":"Tiziano","family":"Villa","sequence":"additional","affiliation":[]},{"given":"Alex","family":"Saldanha","sequence":"additional","affiliation":[]},{"given":"Alberto","family":"Sangiovanni-Vincentelli","sequence":"additional","affiliation":[]}],"member":"37438","reference":[{"issue":"1","key":"1","doi-asserted-by":"crossref","first-page":"131","DOI":"10.1109\/43.486279","article-title":"Global rebuilding of OBDD's avoiding memory requirement maxima","volume":"15","author":"J. Bern","year":"1996","journal-title":"IEEE Trans. CAD Int. Circuits Syst"},{"key":"2","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4613-2821-6","volume-title":"Logic Minimization Algorithms for VLSI Synthesis","author":"R. Brayton","year":"1984"},{"issue":"8","key":"3","doi-asserted-by":"crossref","first-page":"677","DOI":"10.1109\/TC.1986.1676819","article-title":"Graph-based algorithms for Boolean function manipulation","volume":"C(35)","author":"R. Bryant","year":"1986","journal-title":"IEEE Trans. Comput."},{"issue":"3","key":"4","doi-asserted-by":"crossref","DOI":"10.1145\/136035.136043","article-title":"Symbolic Boolean manipulation with ordered binary-decision diagrams","volume":"24","author":"R. Bryant","year":"1992","journal-title":"ACM Comput. Surveys"},{"key":"5","first-page":"663","article-title":"Logic synthesis for large pass transistor circuits","author":"P. Buch","year":"1997"},{"key":"6","first-page":"161","volume-title":"Transforming Boolean relations by symbolic encoding","volume":"987","author":"G. Cabodi","year":"1995"},{"issue":"3","key":"7","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/43.833206","article-title":"Fast exact minimization of BDD's","volume":"19","author":"R. Drechsler","year":"2000","journal-title":"IEEE Trans. CAD Int. Circ. Syst"},{"issue":"3","key":"8","doi-asserted-by":"crossref","first-page":"440","DOI":"10.1109\/TCAD.2004.823342","article-title":"Synthesis of fully testable circuits from BDDs","volume":"23","author":"R. Drechsler","year":"2004","journal-title":"IEEE Trans. CAD Int. Circ. Syst"},{"key":"9","first-page":"294","article-title":"An exact input encoding algorithm for BDDs representing FSMs","author":"W. Gosti","year":"1998"},{"key":"10","volume-title":"Input encoding for minimum BDD size: Theory and experiments","author":"W. Gosti","year":"1997"},{"key":"11","first-page":"325","article-title":"Linear transformations and exact minimization of BDDs","author":"W. Gunther","year":"1998"},{"issue":"14","key":"12","doi-asserted-by":"crossref","first-page":"1321","DOI":"10.1016\/S1383-7621(00)00027-8","article-title":"ACTion: Combining logic synthesis and technology mapping for MUX-based FPGAs","volume":"46","author":"W. Gunther","year":"2000","journal-title":"J. Syst. Archit"},{"issue":"3","key":"13","doi-asserted-by":"crossref","first-page":"252","DOI":"10.1016\/S0019-9958(62)90588-0","article-title":"Some dangers in the state reduction of sequential machines","volume":"5","author":"J. Hartrmanis","year":"1962","journal-title":"Inf. Contr"},{"key":"14","first-page":"254","article-title":"Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool","author":"L. Lavagno","year":"1995"},{"key":"15","first-page":"248","article-title":"Concurrent minimization and state assignment of finite state machines","author":"E. Lee","year":"1984"},{"key":"16","volume-title":"Logic synthesis benchmark circuits for the International Workshop on Logic Synthesis","author":"R. Lisanke","year":"1989"},{"key":"17","first-page":"546","volume-title":"On-the-fly layout generation for PTL macrocells","author":"L. Macchiarulo","year":"2001"},{"issue":"5","key":"18","doi-asserted-by":"crossref","first-page":"521","DOI":"10.1109\/43.845077","article-title":"Linear sifting of decision diagrams and its application in synthesis","volume":"19","author":"C. Meinel","year":"2000","journal-title":"IEEE Trans. CAD Int. Circ. Syst"},{"issue":"1","key":"19","doi-asserted-by":"crossref","first-page":"21","DOI":"10.1051\/ita:1999103","article-title":"On the influence of state encoding on OBDD-representations of finite state machines","volume":"33","author":"C. Meinel","year":"1999","journal-title":"Theoret. Inf. Applic"},{"issue":"1166","key":"20","first-page":"404","article-title":"Local encoding transformations for optimizing OBDD-representations of finite state machines","author":"Ch Meinel","year":"1996 a"},{"key":"21","first-page":"96","volume-title":"State encodings and OBDD-sizes","author":"Ch Meinel","year":"1996 b"},{"key":"22","first-page":"42","article-title":"Dynamic variable ordering for ordered binary decision diagrams","author":"R. Rudell","year":"1993"},{"issue":"5","key":"23","doi-asserted-by":"crossref","first-page":"589","DOI":"10.1109\/43.277632","article-title":"Satisfaction of input and output encoding constraints","volume":"13","author":"A. Saldanha","year":"1994","journal-title":"IEEE Trans. CAD Int. Circ. Syst"},{"key":"24","volume-title":"Synthesis of FSMs: Logic Optimization","author":"T. Villa","year":"1997"},{"key":"25","first-page":"254","article-title":"FSM re-engineering and its application in low power state encoding","volume":"1","author":"L. Yuan","year":"2005"}],"container-title":["International Journal of Applied Mathematics and Computer Science"],"original-title":[],"link":[{"URL":"http:\/\/content.sciendo.com\/view\/journals\/amcs\/17\/1\/article-p113.xml","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.degruyter.com\/view\/j\/amcs.2007.17.issue-1\/v10006-007-0011-6\/v10006-007-0011-6.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T10:26:54Z","timestamp":1709202414000},"score":1,"resource":{"primary":{"URL":"https:\/\/content.sciendo.com\/doi\/10.2478\/v10006-007-0011-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,1]]},"references-count":25,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.2478\/v10006-007-0011-6","relation":{},"ISSN":["1641-876X"],"issn-type":[{"value":"1641-876X","type":"print"}],"subject":[],"published":{"date-parts":[[2007,3,1]]}}}