{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T10:44:18Z","timestamp":1709203458354},"reference-count":14,"publisher":"University of Zielona G\u00f3ra, Poland","issue":"3","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,9,1]]},"abstract":"Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration<\/jats:title>This paper presents research on FPGA based acceleration of HPC applications. The most important goal is to extract a code that can be sped up. A major drawback is the lack of a tool which could do it. HPC applications usually consist of a huge amount of a complex source code. This is one of the reasons why the process of acceleration should be as automated as possible. Another reason is to make use of HLLs (High Level Languages) such as Mitrion-C (Mohl, 2006). HLLs were invented to make the development of HPRC applications faster. Loop profiling is one of the steps to check if the insertion of an HLL to an existing HPC source code is possible to gain acceleration of these applications. Hence the most important step to achieve acceleration is to extract the most time consuming code and data dependency, which makes the code easier to be pipelined and parallelized. Data dependency also gives information on how to implement algorithms in an FPGA circuit with minimal initialization of it during the execution of algorithms.<\/jats:p>","DOI":"10.2478\/v10006-010-0043-1","type":"journal-article","created":{"date-parts":[[2010,9,28]],"date-time":"2010-09-28T01:01:44Z","timestamp":1285635704000},"page":"581-589","source":"Crossref","is-referenced-by-count":1,"title":["Loop profiling tool for HPC code inspection as an efficient method of FPGA based acceleration"],"prefix":"10.61822","volume":"20","author":[{"given":"Marcin","family":"Pietro\u0144","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pawe\u0142","family":"Russek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Kazimierz","family":"Wiatr","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"37438","reference":[{"key":"1","article-title":"An FPGA-oriented target language for HLL compilation","author":"D. Bennett","year":"2006"},{"issue":"12","key":"2","doi-asserted-by":"crossref","first-page":"1654","DOI":"10.1109\/TC.2009.78","article-title":"An automated framework for accelerating numerical algorithms on reconfigurable platform using algorithmic\/architectural optimization","volume":"58","author":"L. Deng","year":"2009","journal-title":"IEEE Transactions on Computers"},{"key":"3","article-title":"Automatic parallelization of sequential C code","author":"P. Gasper","year":"2003"},{"key":"4","article-title":"A high performance application representation for reconfigurable systems","author":"W. Gong","year":"2004"},{"key":"5","first-page":"239","article-title":"Mitrion-C application development on SGI Altix 350\/RC100","author":"V. Kindratenko","year":"2007"},{"key":"6","article-title":"Exploring coarse- and fine-grain parallelism on a high-performance reconfigurable computer","author":"V. Kindratenko","year":"2006"},{"key":"7","first-page":"391","article-title":"Using Mitrion-C to implement floating-point arithmetic on a Cray XD1 supercomputer","author":"K. Liu","year":"2008"},{"issue":"1","key":"8","doi-asserted-by":"crossref","DOI":"10.1145\/1044111.1044115","article-title":"A scheduling algorithm for optimization and planning in high-level synthesis","volume":"10","author":"S. Memik","year":"2005","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"1","key":"9","first-page":"33","article-title":"Accelerating scentific applications using FPGAs","volume":"10","author":"P. Messmer","year":"2006","journal-title":"XCell Journal"},{"key":"10","unstructured":"Mohl, S. (2006). The Mitrion-C programming language, Mitrionics Inc., Second Quarter, pp. 70-73 http:\/\/www.mitrion.com<\/a>"},{"key":"11","article-title":"LoopProf: Dynamic techniques for loop detection and profiling","author":"T. Moseley","year":"2006"},{"key":"12","first-page":"149","article-title":"Methodology of computing acceleration using reconfigurable logic technology in high performance computing","author":"M. Pietro\u0144","year":"2007(a)"},{"key":"13","article-title":"Two electron integrals calculation accelerated with double precision exp() hardware module","author":"M. Pietro\u0144","year":"2007(b)"},{"key":"14","first-page":"44","article-title":"The prospect of computing acceleration using reconfigurable logic technology in huge computational power systems","author":"P. Russek","year":"2006"}],"container-title":["International Journal of Applied Mathematics and Computer Science"],"original-title":[],"link":[{"URL":"http:\/\/content.sciendo.com\/view\/journals\/amcs\/20\/3\/article-p581.xml","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.degruyter.com\/view\/j\/amcs.2010.20.issue-3\/v10006-010-0043-1\/v10006-010-0043-1.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T10:27:54Z","timestamp":1709202474000},"score":1,"resource":{"primary":{"URL":"https:\/\/content.sciendo.com\/doi\/10.2478\/v10006-010-0043-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,9,1]]},"references-count":14,"journal-issue":{"issue":"3"},"URL":"https:\/\/doi.org\/10.2478\/v10006-010-0043-1","relation":{},"ISSN":["1641-876X"],"issn-type":[{"value":"1641-876X","type":"print"}],"subject":[],"published":{"date-parts":[[2010,9,1]]}}}