{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,25]],"date-time":"2026-03-25T05:16:22Z","timestamp":1774415782109,"version":"3.50.1"},"reference-count":24,"publisher":"University of Zielona G\u00f3ra, Poland","issue":"4","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2010,12,1]]},"abstract":"<jats:title>Reduction in the number of LUT elements for control units with code sharing<\/jats:title><jats:p>Two methods are proposed targeted at reduction in the number of look-up table elements in logic circuits of compositional microprogram control units (CMCUs) with code sharing. The methods assume the application of field-programmable gate arrays for the implementation of the combinational part of the CMCU, whereas embedded-memory blocks are used for implementation of its control memory. Both methods are based on the existence of classes of pseudoequivalent operational linear chains in a microprogram to be implemented. Conditions for the application of the proposed methods and examples of design are shown. Results of conducted experiments are given.<\/jats:p>","DOI":"10.2478\/v10006-010-0057-8","type":"journal-article","created":{"date-parts":[[2010,12,22]],"date-time":"2010-12-22T02:43:15Z","timestamp":1292985795000},"page":"751-761","source":"Crossref","is-referenced-by-count":4,"title":["Reduction in the number of LUT elements for control units with code sharing"],"prefix":"10.61822","volume":"20","author":[{"given":"Alexander","family":"Barkalov","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Larysa","family":"Titarenko","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jacek","family":"Bieganowski","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"37438","reference":[{"key":"1","volume-title":"Architectural and Sequential Synthesis of Digital Devices","author":"M. Adamski","year":"2006"},{"key":"2","unstructured":"Altera (2010). Altera corpotation webpage <a target=\"_blank\" href='http:\/\/www.altera.com'>http:\/\/www.altera.com<\/a>"},{"key":"3","volume-title":"Logic and System Design of Digital Systems","author":"S. Baranov","year":"2008"},{"key":"4","doi-asserted-by":"crossref","DOI":"10.1007\/978-3-540-69285-0","volume-title":"Logic Synthesis for Compositonal Microprogram Control Units","author":"A. Barkalov","year":"2008"},{"key":"5","first-page":"397","article-title":"Synthesis of compositional microprogram control units with sharing codes and address decoder","author":"A. Barkalov","year":"2006"},{"key":"6","first-page":"99","article-title":"Cost-efficient synthesis for sequetnial circuits implemented using embedded memory blocks of FPGA's","author":"G. Borowik","year":"2007"},{"key":"7","first-page":"216","article-title":"State assignment method for high speed FSM","author":"R. Czerwi\u0144ski","year":"2004"},{"key":"8","unstructured":"Eastlake, D. and Jones, P. (2001). RFC:3174 US secure hash algorithm 1 (SHA1), <i>Technical report<\/i>, Network Working Group <a target=\"_blank\" href='http:\/\/www.faqs.org\/rfcs\/rfc3174.html'>http:\/\/www.faqs.org\/rfcs\/rfc3174.html<\/a>"},{"issue":"4","key":"9","doi-asserted-by":"crossref","first-page":"415","DOI":"10.1145\/162124.162132","article-title":"State assignment for hardwired VLSI control units","volume":"25","author":"B. Escherman","year":"1993","journal-title":"ACM Computing Surveys"},{"key":"10","doi-asserted-by":"crossref","DOI":"10.1109\/HICSS.2005.291","article-title":"Hardware implementation analysis of the MD5 hash algorithm","author":"K. Jarvinen","year":"2005"},{"key":"11","volume-title":"A Synthesis of Finie State Machines: Functional Optimization","author":"T. Kam","year":"1998"},{"key":"12","volume-title":"Logic Synthesis for PAL-Based Complex Programmable Logic Devices","author":"D. Kania","year":"2004"},{"key":"13","volume-title":"Application of Address Converter for Decreasing Memory Size of Compositional Microprogram Control Unit with Code Sharing","author":"M. Ko\u0142opie\u0144czyk","year":"2008"},{"key":"14","volume-title":"The Design Warrior's Guide to FPGAs","author":"C. Maxfield","year":"2004"},{"key":"15","volume-title":"Synthesis and Optimization of Digital Circuits","author":"G. Micheli","year":"1994"},{"key":"16","volume-title":"Embedded Core Design with FPGAs","author":"Z. Navabi","year":"2007"},{"key":"17","unstructured":"Rivest, R. (1992). RFC:1312 the MD5 message-digest algorithm, <i>Technical report<\/i>, Network Working Group <a target=\"_blank\" href='http:\/\/www.faqs.org\/rfcs\/rfc1312.html'>http:\/\/www.faqs.org\/rfcs\/rfc1312.html<\/a>"},{"key":"18","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4757-3393-8","volume-title":"Functional Decomosition with Application of FPGA Synthesis","author":"C. Scholl","year":"2001"},{"key":"19","unstructured":"Sentovich, E., Singh, K., Lavagno, L., Moon, C., Murgai, R., Saldanha, A., Savoj, H., Stephan, P., Brayton, R. K. and Sangiovanni-Vincentelli, A. L. (1992). SIS: A system for sequential circuit synthesis, <i>Technical Report UCB\/ERL M92\/41<\/i>, EECS Department, University of California, Berkeley, CA."},{"key":"20","volume-title":"Logic Design for Digital Systems on the Base of Programmable Logic Integerated Circuits","author":"V. Solovjev","year":"2008"},{"issue":"2","key":"21","first-page":"201","article-title":"Optimization of compositional microprogram control unit by modification of microinstruction format","volume":"55","author":"L. Titarenko","year":"2009","journal-title":"Electronics and Telecommunication Quarterly"},{"key":"22","unstructured":"Xilinx (2006). <i>Xilinx Synthesis and Simulation Design Guide<\/i>, Xilinx <a target=\"_blank\" href='http:\/\/www.xilinx.com\/itp\/xilinx9\/books\/docs\/sim\/sim.pdf'>http:\/\/www.xilinx.com\/itp\/xilinx9\/books\/docs\/sim\/sim.pdf<\/a>"},{"key":"23","unstructured":"Xilinx (2010). Xilinx corpotation webpage <a target=\"_blank\" href='http:\/\/www.xilinx.com'>http:\/\/www.xilinx.com<\/a>"},{"key":"24","unstructured":"Yang, S. (1991). Logic synthesis and optimization benchmarks user guide, <i>Technical report<\/i>, Microelectronic Center of North Carolina, Research Triangle Park, NC 27709-2889."}],"container-title":["International Journal of Applied Mathematics and Computer Science"],"original-title":[],"link":[{"URL":"http:\/\/content.sciendo.com\/view\/journals\/amcs\/20\/4\/article-p751.xml","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/www.degruyter.com\/view\/j\/amcs.2010.20.issue-4\/v10006-010-0057-8\/v10006-010-0057-8.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,2,29]],"date-time":"2024-02-29T10:27:58Z","timestamp":1709202478000},"score":1,"resource":{"primary":{"URL":"https:\/\/content.sciendo.com\/doi\/10.2478\/v10006-010-0057-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12,1]]},"references-count":24,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.2478\/v10006-010-0057-8","relation":{},"ISSN":["1641-876X"],"issn-type":[{"value":"1641-876X","type":"print"}],"subject":[],"published":{"date-parts":[[2010,12,1]]}}}