{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,20]],"date-time":"2025-02-20T05:16:56Z","timestamp":1740028616949,"version":"3.37.3"},"reference-count":0,"publisher":"IOS Press","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016]]},"abstract":"<jats:p>We report on how we are preparing a seismic imaging code for the Intel Knight's Landing (KNL) Xeon Phi processor. The seismic imaging code in question is a Reverse Time Migration (RTM) code based on an unconventional rotated staggered grid (RSG) method and has undergone a significant amount of Xeon\/Xeon Phi-focused re-engineering at ICHEC. The code uses an explicit finite difference (FD) scheme of variable spatial order, and second order in time, to model wave propagation in three isotropy cases. The code is parallelized with MPI and OpenMP, for wide hardware compatibility. Vectorization and efficient cache utilization were carefully considered in the kernel design, while attempting to maintain portability and maintainability. The stencil-based kernels of the code have low arithmetic intensity and are bound by the main memory bandwidth of the Xeon\/Xeon Phi, which we have successfully alleviated by making highly efficient use of shared last level cache (LLC) on Xeon. The latter optimization is one that throws up some interesting challenges for achieving optimal performance on Xeon Phi, which we discuss further in this report.<\/jats:p>","DOI":"10.3233\/978-1-61499-621-7-585","type":"book-chapter","created":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T15:30:51Z","timestamp":1739979051000},"source":"Crossref","is-referenced-by-count":0,"title":["Preparing a Seismic Imaging Code for the Intel Knights Landing Xeon Phi processor"],"prefix":"10.3233","author":[{"family":"Civario Gilles","sequence":"additional","affiliation":[]},{"family":"Delaney Se&aacute;n","sequence":"additional","affiliation":[]},{"family":"Lysaght Michael","sequence":"additional","affiliation":[]}],"member":"7437","container-title":["Advances in Parallel Computing","Parallel Computing: On the Road to Exascale"],"original-title":[],"deposited":{"date-parts":[[2025,2,19]],"date-time":"2025-02-19T15:33:47Z","timestamp":1739979227000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.medra.org\/servlet\/aliasResolver?alias=iospressISBN&isbn=978-1-61499-620-0&spage=585&doi=10.3233\/978-1-61499-621-7-585"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016]]},"references-count":0,"URL":"https:\/\/doi.org\/10.3233\/978-1-61499-621-7-585","relation":{},"ISSN":["0927-5452"],"issn-type":[{"value":"0927-5452","type":"print"}],"subject":[],"published":{"date-parts":[[2016]]}}}