{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,16]],"date-time":"2026-05-16T23:41:51Z","timestamp":1778974911448,"version":"3.51.4"},"reference-count":67,"publisher":"SAGE Publications","issue":"1","license":[{"start":{"date-parts":[[2024,10,18]],"date-time":"2024-10-18T00:00:00Z","timestamp":1729209600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["Integrated Computer-Aided Engineering"],"published-print":{"date-parts":[[2025,2]]},"abstract":"<jats:p>This study presents a high-level simulator for Network-on-Chip (NoC), designed for many-core architectures, and integrated with the PlatEMO platform. The motivation for developing this tool arose from the need to evaluate the behavior of application mapping algorithms and the routing, both aspects are essential in the implementation and design of NoC architectures. This analysis underscored the importance of having effective NoC simulators as tools that allow for studying and comparing various network technologies while ensuring a controlled simulation environment. During this investigation and evaluation, some simulators, such as Noxim, NoCTweak, and NoCmap, among others, offered configurable parameters for application traffic, options to synthetically define topology and packet traffic patterns. Additionally, they include mapping options that optimize latency and energy consumption, routing algorithms, technological settings such as the CMOS process, and measurement options for evaluating performance metrics such as throughput and power usage. However, while these simulators meet detailed technical demands, they are mostly restricted to analyzing the low-level elements of the architecture, thus hindering quick and easy under- standing for non-specialists. This insight underscored the challenge in developing a tool that balances detailed analysis with a comprehensive learning perspective, considering the specific restrictions of each simulator analyzed. Experiments demonstrated the proposed simulator efficacy in handling algorithms like GA, PSO, and SA variant, and, surprisingly, revealed limitations of the XY algorithm in Mesh topologies, indicating the need for further investigation to confirm these findings. Future work will expand the simulator functionalities, incorporating a broader range of algorithms and performance metrics, to establish it as an indispensable tool for research and development in NoCs.<\/jats:p>","DOI":"10.3233\/ica-240743","type":"journal-article","created":{"date-parts":[[2024,8,20]],"date-time":"2024-08-20T10:55:21Z","timestamp":1724151321000},"page":"57-73","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":3,"title":["A high-level simulator for Network-on-Chip"],"prefix":"10.1177","volume":"32","author":[{"given":"Paulo Cesar Donizeti","family":"Paris","sequence":"first","affiliation":[{"name":"Federal University of Sao Carlos","place":["Brazil"]}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Emerson Carlos","family":"Pedrino","sequence":"additional","affiliation":[{"name":"Federal University of Sao Carlos","place":["Brazil"]}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[2024,10,18]]},"reference":[{"key":"e_1_3_2_2_1","doi-asserted-by":"publisher","DOI":"10.3233\/ICA-230717"},{"key":"e_1_3_2_3_1","doi-asserted-by":"crossref","unstructured":"Joardar B Arka A Doppa J Pande P Li H Chakrabarty K. Heterogeneous Manycore Architectures Enabled by Processing-in-Memory for Deep Learning: From CNNs to GNNs: (ICCAD Special Session Paper). In: 2021 IEEE\/ACM International Conference On Computer Aided Design (ICCAD). IEEE; 2021. pp. 1-7.","DOI":"10.1109\/ICCAD51958.2021.9643559"},{"key":"e_1_3_2_4_1","article-title":"Many-Core Computing: Hardware and Software","author":"Al-Hashimi B","year":"2019","unstructured":"Al-Hashimi B, Merrett G. Many-Core Computing: Hardware and Software. Institution of Engineering & Technology, 2019.","journal-title":"Institution of Engineering & Technology"},{"key":"e_1_3_2_5_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.simpat.2016.12.014"},{"key":"e_1_3_2_6_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2019.2895701"},{"key":"e_1_3_2_7_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2021.3108475"},{"key":"e_1_3_2_8_1","doi-asserted-by":"publisher","DOI":"10.1109\/2.976921"},{"key":"e_1_3_2_9_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2017.07.004"},{"key":"e_1_3_2_10_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.compeleceng.2022.108404"},{"key":"e_1_3_2_11_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2022.102762"},{"key":"e_1_3_2_12_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2020.09.013"},{"key":"e_1_3_2_13_1","doi-asserted-by":"crossref","unstructured":"Sharma A Srivastava S Rautela P Joshi B. Metaheuristics-Based Routing Optimization in On-Chip Network. In: Proceedings of the 2023 Fifteenth International Conference on Contemporary Computing IC3-2023. Noida India: Association for Computing Machinery; 2023. pp. 18-23.","DOI":"10.1145\/3607947.3607953"},{"key":"e_1_3_2_14_1","doi-asserted-by":"publisher","DOI":"10.1061\/(ASCE)0733-9445(1997)123:7(880)"},{"key":"e_1_3_2_15_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218213014300026"},{"key":"e_1_3_2_16_1","doi-asserted-by":"publisher","DOI":"10.1177\/109434209300700206"},{"key":"e_1_3_2_17_1","doi-asserted-by":"publisher","DOI":"10.1061\/(ASCE)0733-9445(1995)121:10(1448)"},{"key":"e_1_3_2_18_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218213014300014"},{"key":"e_1_3_2_19_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218001415390012"},{"key":"e_1_3_2_20_1","doi-asserted-by":"publisher","DOI":"10.1142\/S0218213016300015"},{"key":"e_1_3_2_21_1","doi-asserted-by":"publisher","DOI":"10.1111\/exsy.12357"},{"key":"e_1_3_2_22_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.eswa.2019.02.026"},{"key":"e_1_3_2_23_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.asoc.2019.105887"},{"key":"e_1_3_2_24_1","doi-asserted-by":"publisher","DOI":"10.1061\/(ASCE)0893-1321(1994)7:3(297)"},{"key":"e_1_3_2_25_1","doi-asserted-by":"publisher","DOI":"10.1061\/(ASCE)0733-9445(1995)121:10(1448)"},{"key":"e_1_3_2_26_1","doi-asserted-by":"crossref","unstructured":"Sambangi R Pandey A Manna K Mahapatra S Chattopadhyay S. Application Mapping Onto Manycore Processor Architectures Using Active Search Framework. IEEE Transactions on Very Large Scale Integration (VLSI) Systems.2023; 31(06): 789-801.","DOI":"10.1109\/TVLSI.2023.3239850"},{"key":"e_1_3_2_27_1","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cdt.2017.0068"},{"key":"e_1_3_2_28_1","unstructured":"Achballah AB Saoud SB. A survey of network-on-chip tools. arXiv preprint arXiv13122976. 2013."},{"key":"e_1_3_2_29_1","unstructured":"Tran A Baas B. NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip. VLSI Computation Lab ECE Department University of California Davis; 2012; ECE-VCL-2012-2."},{"key":"e_1_3_2_30_1","first-page":"162","article-title":"Noxim: An open, extensible and cycle-accurate network on chip simulator","author":"Catania V","year":"2015","unstructured":"Catania V, Mineo A, Monteleone S, Palesi M, Patti D. Noxim: An open, extensible and cycle-accurate network on chip simulator. In: Proceedings of [nome da confer\u00eancia];2015; pp.\u00a0162-163.","journal-title":"In: Proceedings of [nome da confer\u00eancia];"},{"key":"e_1_3_2_31_1","first-page":"16","article-title":"NIRGAM: a simulator for NoC interconnect routing and application modeling","author":"Jain L","year":"2007","unstructured":"Jain L, Al-Hashimi B, Gaur M, Laxmi V, Narayanan A. NIRGAM: a simulator for NoC interconnect routing and application modeling. In: Design, automation and test in Europe conference. IEEE;2007; pp.\u00a016-20.","journal-title":"In: Design, automation and test in Europe conference. IEEE;"},{"key":"e_1_3_2_32_1","unstructured":"Lu Z Thid R Millberg M Nilsson E Jantsch A. NNSE: Nostrum network-on-chip simulation environment. In: Proceedings of the SSoCC; 2005; p.\u00a01."},{"key":"e_1_3_2_33_1","unstructured":"Jiang N Michelogiannakis G Becker D Towles B Dally WJ. Booksim 2.0 user\u2019s guide. Standford University. 2010; p.\u00a0q1."},{"key":"e_1_3_2_34_1","doi-asserted-by":"crossref","unstructured":"Hu J Marculescu R. Energy-aware mapping for tile-based NoC architectures under performance constraints. In: Proceedings of the 2003 Asia and South Pacific Design Automation Conference; 2003. pp.\u00a0233-239.","DOI":"10.1145\/1119772.1119818"},{"key":"e_1_3_2_35_1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2005.844106"},{"key":"e_1_3_2_36_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2402197"},{"key":"e_1_3_2_37_1","doi-asserted-by":"crossref","unstructured":"Liu Y Peng B Zhu X Wang W Zhou Q Wang S et al. Automatic endometrial segmentation in ultrasound images using deep learning. In: 2022 IEEE 15th International Symposium on Embedded Multicore\/Many-core Systems-on-Chip (MCSoC). IEEE; 2022. pp. 67-71.","DOI":"10.1109\/MCSoC57363.2022.00020"},{"key":"e_1_3_2_38_1","doi-asserted-by":"crossref","unstructured":"Mathew A Amudha P Sivakumari S. Deep Learning Techniques: An Overview. In: Hassanien AE Bhatnagar R Darwish A editors. Advanced Machine Learning Technologies and Applications. Singapore: Springer Singapore; 2021; pp.\u00a0599-608.","DOI":"10.1007\/978-981-15-3383-9_54"},{"key":"e_1_3_2_39_1","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2009.9"},{"key":"e_1_3_2_40_1","doi-asserted-by":"crossref","unstructured":"Kazempour V Fedorova A Alagheband P. Performance implications of cache affinity on multicore processors. In: Euro-Par 2008\u2013Parallel Processing: 14th International Euro-Par Conference Las Palmas de Gran Canaria Spain August 26\u201329 2008. Proceedings 14. Springer; 2008. pp.\u00a0151-161.","DOI":"10.1007\/978-3-540-85451-7_17"},{"key":"e_1_3_2_41_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jpdc.2019.12.011"},{"key":"e_1_3_2_42_1","doi-asserted-by":"publisher","DOI":"10.1108\/IJPCC-07-2019-0053"},{"key":"e_1_3_2_43_1","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9010006"},{"key":"e_1_3_2_44_1","doi-asserted-by":"crossref","unstructured":"Wang X Xi J Wang Y Bogdan P Nazarian S. An Efficient Task Mapping for Manycore Systems. In: 2020 IEEE International Symposium on Circuits and Systems (ISCAS); 2020. pp.\u00a01-4.","DOI":"10.1109\/ISCAS45731.2020.9181267"},{"key":"e_1_3_2_45_1","doi-asserted-by":"publisher","DOI":"10.12785\/IJCDS\/060201"},{"key":"e_1_3_2_46_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.jnca.2021.103319"},{"key":"e_1_3_2_47_1","doi-asserted-by":"publisher","DOI":"10.3390\/s21155102"},{"key":"e_1_3_2_48_1","doi-asserted-by":"crossref","unstructured":"Dai Q Liu Q Shen J Sun M. Modified genetic algorithm-based method on low-power mapping in network-on-chip. In: 2015 International Conference on Applied Science and Engineering Innovation; 2015. pp.\u00a01837-1846.","DOI":"10.2991\/asei-15.2015.366"},{"key":"e_1_3_2_49_1","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2018.2811716"},{"key":"e_1_3_2_50_1","doi-asserted-by":"crossref","unstructured":"Reddy B James A Kumar A. Fault-Tolerant Core Mapping for NoC based architectures with improved Performance and Energy Efficiency. In: 2022 29th IEEE International Conference on Electronics Circuits and Systems (ICECS); 2022. pp. 1-4.","DOI":"10.1109\/ICECS202256217.2022.9970825"},{"key":"e_1_3_2_51_1","doi-asserted-by":"publisher","DOI":"10.32604\/iasc.2022.025290"},{"key":"e_1_3_2_52_1","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/JPHOT.2018.2796094","article-title":"Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip","author":"Guo P","year":"2018","unstructured":"Guo P, Hou W, Guo L, Yang Q, Ge Y, Liang H. Low Insertion Loss and Non-Blocking Microring-Based Optical Router for 3D Optical Network-on-Chip. IEEE Photonics Journal.2018; 01; pp.\u00a01-1.","journal-title":"IEEE Photonics Journal."},{"key":"e_1_3_2_53_1","unstructured":"Wang H Zhu X Peh L Malik S. Orion: A Power-Performance Simulator for Interconnection Networks. In: Proceedings of the 35th Annual ACM\/IEEE International Symposium on Microarchitecture; 2002. pp.\u00a0294-305."},{"key":"e_1_3_2_54_1","doi-asserted-by":"crossref","unstructured":"Kahng A Li B Peh L Samadi K. Orion 20: A Fast and Accurate NoC Power and Area Model for Early-Stage Design Space Exploration. In: Proceedings of the Conference on Design Automation and Test in Europe; 2009; pp.\u00a0423-428.","DOI":"10.1109\/DATE.2009.5090700"},{"key":"e_1_3_2_55_1","doi-asserted-by":"publisher","DOI":"10.1109\/LES.2015.2402197"},{"key":"e_1_3_2_56_1","doi-asserted-by":"crossref","unstructured":"Ojeda B Saenz M Alulema V Alulema D. Analysis of a Network Interface for an On-Chip Network Architecture. In: Robles-Bykbaev V Mula J Reynoso-Meza G editors. Intelligent Technologies: Design and Applications for Society. Springer Nature Switzerland; 2023; pp. 72-80.","DOI":"10.1007\/978-3-031-24327-1_7"},{"key":"e_1_3_2_57_1","doi-asserted-by":"crossref","unstructured":"Xu C Li Y Liu Z Xin M Yao H Xiong D et al. A Region-Tree Based Fault-tolerant Routing Algorithm for Network-on-Chip. In: 2022 IEEE 2nd International Conference on Power Electronics and Computer Applications (ICPECA); 2022. pp.\u00a072-76.","DOI":"10.1109\/ICPECA53709.2022.9718885"},{"key":"e_1_3_2_58_1","doi-asserted-by":"crossref","unstructured":"Umapathy S Shah M Wang N. Encircle routing: An efficient deterministic network on chip routing algorithm. In: 2018 IEEE 8th Annual Computing and Communication Workshop and Conference (CCWC). IEEE; 2018. pp.\u00a0895-899.","DOI":"10.1109\/CCWC.2018.8301661"},{"key":"e_1_3_2_59_1","doi-asserted-by":"crossref","unstructured":"Yue K Ghalim S Li Z Lockom F Ren S Zhang L et al. A greedy approach to tolerate defect cores for multimedia applications. In: 2011 9th IEEE Symposium on Embedded Systems for Real-Time Multimedia; 2011. pp.\u00a0112-119.","DOI":"10.1109\/ESTIMedia.2011.6088517"},{"key":"e_1_3_2_60_1","doi-asserted-by":"crossref","unstructured":"Millberg M Nilsson E Thid R Kumar S Jantsch A. The Nostrum backbone-a communication protocol stack for Networks on Chip. In: 17th International Conference on VLSI Design. Proceedings. 2004. pp.\u00a0693-696.","DOI":"10.1109\/ICVD.2004.1261005"},{"key":"e_1_3_2_61_1","doi-asserted-by":"crossref","unstructured":"Kumar A Talawar B. Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks. In: 2018 Eleventh International Conference on Contemporary Computing (IC3); 2018. pp.\u00a01-6.","DOI":"10.1109\/IC3.2018.8530505"},{"key":"e_1_3_2_62_1","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2021.104370"},{"key":"e_1_3_2_63_1","doi-asserted-by":"crossref","unstructured":"Dick R Rhodes D Wolf W. TGFF: task graphs for free. In: Proceedings of the Sixth International Workshop on Hardware\/Software Codesign. (CODES\/CASHE\u201998); 1998. pp. 97-101.","DOI":"10.1145\/278241.278309"},{"key":"e_1_3_2_64_1","unstructured":"Brown JW. Adaptive Network on Chip Routing using the Turn Model. In: Proceedings of the [Computer Science]; 2013; p.\u00a01. Available from: https\/\/api.semanticscholar.org\/CorpusID:111026217."},{"key":"e_1_3_2_65_1","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.130"},{"key":"e_1_3_2_66_1","doi-asserted-by":"publisher","DOI":"10.1109\/MCI.2017.2742868"},{"key":"e_1_3_2_67_1","doi-asserted-by":"crossref","unstructured":"Zhang S Liu P Guo X Wang J Qin S Tang Y. An Improved Tabu Search Algorithm for Multi-robot Hybrid Disassembly Line Balancing Problems. In: 2022 International Conference on Cyber-Physical Social Intelligence (ICCSI); 2022. pp.\u00a0315-320.","DOI":"10.1109\/ICCSI55536.2022.9970618"},{"key":"e_1_3_2_68_1","unstructured":"Tajary A Morshedlou H. A Simulated Annealing-based Throughput-aware Task Mapping Algorithm for Manycore Processors. J AI Data Min.2022; 10(3): 311-320."}],"container-title":["Integrated Computer-Aided Engineering"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/ICA-240743","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/full-xml\/10.3233\/ICA-240743","content-type":"application\/xml","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/ICA-240743","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T09:14:55Z","timestamp":1777454095000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.3233\/ICA-240743"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,10,18]]},"references-count":67,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2025,2]]}},"alternative-id":["10.3233\/ICA-240743"],"URL":"https:\/\/doi.org\/10.3233\/ica-240743","relation":{},"ISSN":["1069-2509","1875-8835"],"issn-type":[{"value":"1069-2509","type":"print"},{"value":"1875-8835","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,10,18]]}}}