{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,11]],"date-time":"2026-02-11T14:01:16Z","timestamp":1770818476431,"version":"3.50.1"},"reference-count":0,"publisher":"SAGE Publications","issue":"4","license":[{"start":{"date-parts":[[2014,1,1]],"date-time":"2014-01-01T00:00:00Z","timestamp":1388534400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":["journals.sagepub.com"],"crossmark-restriction":true},"short-container-title":["Journal of Intelligent &amp; Fuzzy Systems"],"published-print":{"date-parts":[[2014,4]]},"abstract":"<jats:p>In this article, an analog fully programmable membership function generator (MFG) is presented. It is capable of generating Gaussian, Triangular and Trapezoidal shapes as well as S or Z shapes. For omitting noise disturbances, differential structures are utilized in input and output stages which are in voltage mode and current mode, respectively. In contrast with conventional MFGs which are controlled digitally or by mixed signal approaches, this structure is a fully programmable analog MFG. It is capable of modifying slope, position and height of output's current. The most distinguishing features of this MFG are its capability of generating ultra-high speed outputs reaching speeds as high as 200 MHz and consuming a very low amount of power. Due to the simple structure of this MFG, it consumes a small active area at the size of 20 \u03bcm \u00d7 30 \u03bcm. It is constructed of only 16 transistors. This MFG has been designed in 0.35 \u03bcm CMOS technology. The simulations have been done with Hspice using TSMC, BSIM3 (V3.1) model.<\/jats:p>","DOI":"10.3233\/ifs-130862","type":"journal-article","created":{"date-parts":[[2019,12,2]],"date-time":"2019-12-02T18:26:06Z","timestamp":1575311166000},"page":"1823-1832","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":1,"title":["A circuit implementation of an ultra high speed, low power analog fully programmable MFG"],"prefix":"10.1177","volume":"26","author":[{"given":"Mohammad","family":"Tohidi","sequence":"first","affiliation":[{"name":"Microelectronics Research Laboratory, Urmia University, Urmia, Iran"}]},{"given":"Alireza","family":"Abolhasani","sequence":"additional","affiliation":[{"name":"Microelectronics Research Laboratory, Urmia University, Urmia, Iran"}]},{"given":"Abdollah","family":"Khoei","sequence":"additional","affiliation":[{"name":"Microelectronics Research Laboratory, Urmia University, Urmia, Iran"}]},{"given":"Khayrollah","family":"Hadidi","sequence":"additional","affiliation":[{"name":"Microelectronics Research Laboratory, Urmia University, Urmia, Iran"}]}],"member":"179","published-online":{"date-parts":[[2014,1]]},"container-title":["Journal of Intelligent &amp; Fuzzy Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/IFS-130862","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/IFS-130862","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,2,11]],"date-time":"2026-02-11T12:25:52Z","timestamp":1770812752000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.3233\/IFS-130862"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,1]]},"references-count":0,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2014,4]]}},"alternative-id":["10.3233\/IFS-130862"],"URL":"https:\/\/doi.org\/10.3233\/ifs-130862","relation":{},"ISSN":["1064-1246","1875-8967"],"issn-type":[{"value":"1064-1246","type":"print"},{"value":"1875-8967","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,1]]}}}