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This analog multiplier\/divider circuit operates based on the square-law characteristic of a MOS transistor operated in the saturation region. The proposed circuits are designed in 0.18\u03bcm CMOS technology with a power supply of 2 Volt. The maximum delay for the proposed circuit is 50.7\u200ans that restricts the inference speed of the total fuzzy logic controller to 20 MFLIPS in its turn. The maximum power consumption of this circuit is about 626\u03bcW and can be implemented in 84\u03bcm\u00d736\u03bcm. The functionality of the proposed multiplier\/divider in the defuzzifier block of a typical (3\u00d73) FLC was evaluated and results indicate that the percentage of root mean squarer error (RMSE) of the output surface is 1.08% of the full scale output. To obtain the ideal output surface MATLAB software has been utilized.<\/jats:p>","DOI":"10.3233\/ifs-151680","type":"journal-article","created":{"date-parts":[[2015,11,10]],"date-time":"2015-11-10T11:36:11Z","timestamp":1447155371000},"page":"2029-2038","update-policy":"https:\/\/doi.org\/10.1177\/sage-journals-update-policy","source":"Crossref","is-referenced-by-count":2,"title":["CMOS implementation of a novel analog multiplier\/divider to realize centroid strategy in defuzzifier block"],"prefix":"10.1177","volume":"29","author":[{"given":"Naser","family":"Beyraghi","sequence":"first","affiliation":[{"name":"Urmia University","place":["Iran"]}]},{"given":"Abdollah","family":"Khoei","sequence":"additional","affiliation":[{"name":"Urmia University","place":["Iran"]}]}],"member":"179","published-online":{"date-parts":[[2015,8]]},"reference":[{"key":"e_1_3_1_2_2","unstructured":"Sugeno M 1985 Industrial Applications of Fuzzy Control North-Holland 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