{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,21]],"date-time":"2026-04-21T22:47:01Z","timestamp":1776811621857,"version":"3.51.2"},"reference-count":20,"publisher":"European Society of Computational Methods in Sciences and Engineering","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["JCM"],"published-print":{"date-parts":[[2022,3,28]]},"abstract":"<jats:p>The need to implement high-speed Signal processing applications in which multiplication and division play a vital role made logarithmic arithmetic a prominent contender over the traditional arithmetic operations in recent years. But the logarithm and antilogarithm converters are the bottlenecks. In order to reduce the logarithmic conversion complexity, several works have been introduced from time to time for correcting the error in Mitchell\u2019s algorithm but at the cost of hardware. In this work, we propose a 32-bit binary to the binary logarithmic converter with a simple correction circuit compared with existing techniques. Unlike the current methods that use the linear piece-wise approximation in the mantissa, we propose a weighted average method to correct the error in Mitchell\u2019s approximation. The maximum error percentage from the proposed work is 0.91%, which is 16.9% of Mitchell\u2019s error percentage.<\/jats:p>","DOI":"10.3233\/jcm-215778","type":"journal-article","created":{"date-parts":[[2021,12,21]],"date-time":"2021-12-21T12:10:05Z","timestamp":1640088605000},"page":"511-527","source":"Crossref","is-referenced-by-count":0,"title":["Hardware efficient circuit for low error logarithmic converter"],"prefix":"10.66113","volume":"22","author":[{"given":"Bhaskara Rao","family":"Jammu","sequence":"first","affiliation":[{"name":"Department of ECE, GVP College of Engineering (A), Visakhapatnam, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L. Guna Sekhar Sai","family":"Harsha","sequence":"additional","affiliation":[{"name":"Department of ECE, GVP College of Engineering (A), Visakhapatnam, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Nalini","family":"Bodasingi","sequence":"additional","affiliation":[{"name":"Department of ECE, JNTUK UCEV, Vizianagaram, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sreehari","family":"Veeramachaneni","sequence":"additional","affiliation":[{"name":"Department of ECE, GRIET, Hyderabad, India"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Noor Mohammad","family":"SK","sequence":"additional","affiliation":[{"name":"Department of CSE, IIITDM Kancheepuram, Tamilnadu, India"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"55691","reference":[{"key":"10.3233\/JCM-215778_ref1","doi-asserted-by":"crossref","unstructured":"Ramin Tajallipour and Khan A Wahid, Error-free algorithm and architecture of radix-10 logarithmic converter, Computers Electrical Engineering, 2010, 36(6): 1066\u20131074.","DOI":"10.1016\/j.compeleceng.2010.03.009"},{"issue":"1","key":"10.3233\/JCM-215778_ref2","first-page":"23","article-title":"An iterative logarithmic multiplier","volume":"36","author":"BabiA","year":"2011","journal-title":"Microprocessors and Microsystems"},{"key":"10.3233\/JCM-215778_ref3","doi-asserted-by":"crossref","first-page":"512","DOI":"10.1109\/TEC.1962.5219391","article-title":"Computer multiplication and division using binary logarithms","author":"Mitchell","year":"1962","journal-title":"IRE Transactions on Electronic Computers"},{"issue":"6","key":"10.3233\/JCM-215778_ref4","doi-asserted-by":"crossref","first-page":"863","DOI":"10.1109\/PGEC.1965.264080","article-title":"Computation of the base two logarithm of binary numbers","volume":"14","author":"Combet","year":"1965","journal-title":"IEEE Transactions on Electronic Computers"},{"issue":"2","key":"10.3233\/JCM-215778_ref5","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1109\/T-C.1970.222874","article-title":"Generation of products and quotients using approximate binary logarithms for digital filtering applications","volume":"19","author":"Hall","year":"1970","journal-title":"IEEE Transactions on Computers"},{"issue":"3","key":"10.3233\/JCM-215778_ref6","first-page":"388","article-title":"A fast, low-power logarithm approximation with cmos vlsi implementation","volume":"1","author":"SanGregory","year":"1999","journal-title":"42nd Midwest Symposium on Circuits and Systems (Cat. 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