{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,2]],"date-time":"2025-05-02T04:13:42Z","timestamp":1746159222397,"version":"3.40.4"},"reference-count":0,"publisher":"SAGE Publications","issue":"3","license":[{"start":{"date-parts":[[2009,8,1]],"date-time":"2009-08-01T00:00:00Z","timestamp":1249084800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/journals.sagepub.com\/page\/policies\/text-and-data-mining-license"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Journal of Embedded Computing"],"published-print":{"date-parts":[[2009,8]]},"abstract":"<jats:p> The increase of within-die variations and the design margin growth are creating a need for statistical design methodologies. This paper proposes a simple statistical timing analysis method considering the lot to lot process shifts that occur during production. This method is validated for 90~nm and 65~nm process. Finally, this statistical timing analysis is applied to evaluate, on basic ring oscillators and combinational paths, the timing margins introduced at the design level by the traditional corner based approach. <\/jats:p>","DOI":"10.3233\/jec-2009-0094","type":"journal-article","created":{"date-parts":[[2019,12,3]],"date-time":"2019-12-03T13:05:56Z","timestamp":1575378356000},"page":"221-229","source":"Crossref","is-referenced-by-count":0,"title":["Timing margin evaluation with a simple statistical timing analysis flow"],"prefix":"10.1177","volume":"3","author":[{"given":"V.","family":"Migairou","sequence":"first","affiliation":[{"name":"STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Wilson","sequence":"additional","affiliation":[{"name":"STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S.","family":"Engels","sequence":"additional","affiliation":[{"name":"STMicroelectronics Design Department 850 rue J. Monnet, 38926, Crolles, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Z.","family":"Wu","sequence":"additional","affiliation":[{"name":"LIRMM, UMR CNRS\/Universit\u00e9 de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Azemard","sequence":"additional","affiliation":[{"name":"LIRMM, UMR CNRS\/Universit\u00e9 de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P.","family":"Maurine","sequence":"additional","affiliation":[{"name":"LIRMM, UMR CNRS\/Universit\u00e9 de Montpellier II, (C5506), 161 rue Ada, 34392, Montpellier, France"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"179","published-online":{"date-parts":[[2009,8,1]]},"container-title":["Journal of Embedded Computing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/JEC-2009-0094","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/journals.sagepub.com\/doi\/pdf\/10.3233\/JEC-2009-0094","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T17:36:11Z","timestamp":1746120971000},"score":1,"resource":{"primary":{"URL":"https:\/\/journals.sagepub.com\/doi\/10.3233\/JEC-2009-0094"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2009,8]]},"references-count":0,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2009,8]]}},"alternative-id":["10.3233\/JEC-2009-0094"],"URL":"https:\/\/doi.org\/10.3233\/jec-2009-0094","relation":{},"ISSN":["1740-4460","1875-9025"],"issn-type":[{"type":"print","value":"1740-4460"},{"type":"electronic","value":"1875-9025"}],"subject":[],"published":{"date-parts":[[2009,8]]}}}