{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T14:22:57Z","timestamp":1761402177192,"version":"build-2065373602"},"reference-count":24,"publisher":"MDPI AG","issue":"6","license":[{"start":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T00:00:00Z","timestamp":1622505600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61525401"],"award-info":[{"award-number":["61525401"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Algorithms"],"abstract":"<jats:p>Applications have different preferences for caches, sometimes even within the different running phases. Caches with fixed parameters may compromise the performance of a system. To solve this problem, we propose a real-time adaptive reconfigurable cache based on the decision tree algorithm, which can optimize the average memory access time of cache without modifying the cache coherent protocol. By monitoring the application running state, the cache associativity is periodically tuned to the optimal cache associativity, which is determined by the decision tree model. This paper implements the proposed decision tree-based adaptive reconfigurable cache in the GEM5 simulator and designs the key modules using Verilog HDL. The simulation results show that the proposed decision tree-based adaptive reconfigurable cache reduces the average memory access time compared with other adaptive algorithms.<\/jats:p>","DOI":"10.3390\/a14060176","type":"journal-article","created":{"date-parts":[[2021,6,1]],"date-time":"2021-06-01T15:58:44Z","timestamp":1622563124000},"page":"176","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Decision Tree-Based Adaptive Reconfigurable Cache Scheme"],"prefix":"10.3390","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1018-0271","authenticated-orcid":false,"given":"Wei","family":"Zhu","sequence":"first","affiliation":[{"name":"State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaoyang","family":"Zeng","sequence":"additional","affiliation":[{"name":"State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2021,6,1]]},"reference":[{"key":"ref_1","unstructured":"Hennessy, J.L., and Patterson, D.A. (2011). Computer Architecture: A Quantitative Approach, Elsevier. [5th ed.]."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Adegbija, T., Gordon-Ross, A., and Munir, A. (October, January 30). Dynamic phase-based tuning for embedded systems using phase distance mapping. Proceedings of the 2012 IEEE 30th International Conference on Computer Design (ICCD), Montreal, QC, Canada.","DOI":"10.1109\/ICCD.2012.6378653"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"El-Sayed, N., Mukkara, A., Tsai, P.-A., Kasture, H., Ma, X., and Sanchez, D. (2018, January 24\u201328). KPart: A hybrid cache partitioning-sharing technique for commodity multicores. Proceedings of the 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), Vienna, Austria.","DOI":"10.1109\/HPCA.2018.00019"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Aupy, G., Benoit, A., Goglin, B., Pottier, L., and Robert, Y. (2018, January 10\u201313). Co-Scheduling HPC Workloads on Cache-Partitioned CMP Platforms. Proceedings of the 2018 IEEE International Conference on Cluster Computing (CLUSTER), Belfast, UK.","DOI":"10.1109\/CLUSTER.2018.00052"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1109\/TVLSI.2008.2002459","article-title":"Fast Configurable-Cache Tuning with a Unified Second-Level Cache","volume":"17","author":"Vahid","year":"2009","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_6","first-page":"1","article-title":"The Design of Reconfigurable Cache Scheme in Multi-core Processor","volume":"33","author":"Xie","year":"2016","journal-title":"Microelectron. Comput."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Hsu, P.-Y., and Hwang, T. (2013, January 18\u201321). Thread-criticality aware dynamic cache reconfiguration in multi-core system. Proceedings of the 2013 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, CA, USA.","DOI":"10.1109\/ICCAD.2013.6691151"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Huang, Y., and Mishra, P. (2017, January 5\u20138). Vulnerability-aware energy optimization using reconfigurable caches in multicore systems. Proceedings of the 2017 IEEE International Conference on Computer Design (ICCD), Boston, MA, USA.","DOI":"10.1109\/ICCD.2017.44"},{"key":"ref_9","unstructured":"Huang, Y., and Mishra, P. (2016, January 15\u201316). Reliability and energy-aware cache reconfiguration for embedded systems. Proceedings of the 2016 17th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1145\/3309762","article-title":"Cache Reconfiguration Using Machine Learning for Vulnerability-aware Energy Optimization","volume":"18","author":"Ahmed","year":"2019","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"60","DOI":"10.1145\/3350422","article-title":"Efficient Cache Reconfiguration Using Machine Learning in NoC-Based Many-Core CMPs","volume":"24","author":"Charles","year":"2019","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"28","DOI":"10.1145\/2220336.2220340","article-title":"Dynamic Cache Reconfiguration for Soft Real-Time Systems","volume":"11","author":"Wang","year":"2012","journal-title":"ACM Trans. Embed. Comput. Syst."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Chen, Y.-H., Wu, A.C.-H., and Hwang, T. (2021, January 18\u201321). A Dynamic Link-latency Aware Cache Replacement Policy (DLRP). Proceedings of the 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan.","DOI":"10.1145\/3394885.3431420"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"445","DOI":"10.1109\/TCAD.2017.2712666","article-title":"Replacement Policy Adaptable Miss Curve Estimation for Efficient Cache Partitioning","volume":"37","author":"Lee","year":"2018","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Warrier, T.S., Anupama, B., and Mutyam, M. (2013, January 19\u201322). An application-aware cache replacement policy for last-level caches. Proceedings of the International Conference on Architecture of Computing Systems, Prague, Czech Republic.","DOI":"10.1007\/978-3-642-36424-2_18"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Danielsson, J., J\u00e4gemar, M., Behnam, M., Seceleanu, T., and Sj\u00f6din, M. (2019, January 14\u201317). Run-time cache-partition controller for multi-core systems. Proceedings of the IECON 2019\u201445th Annual Conference of the IEEE Industrial Electronics Society, Lisbon, Portugal.","DOI":"10.1109\/IECON.2019.8926758"},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Tsai, P.-A., Beckmann, N., and Sanchez, D. (2017, January 24\u201328). Jenga: Software-defined cache hierarchies. Proceedings of the 44th Annual International Symposium on Computer Architecture, Toronto, ON, Canada.","DOI":"10.1145\/3079856.3080214"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"2206","DOI":"10.1109\/TCAD.2019.2935065","article-title":"AdaMD: Adaptive Mapping and DVFS for Energy-Efficient Heterogeneous Multicores","volume":"39","author":"Basireddy","year":"2020","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"DiTomaso, D., Sikder, A., Kodi, A., and Louri, A. (2017, January 27\u201331). Machine learning enabled power-aware network-on-chip design. Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), Lausanne, Switzerland.","DOI":"10.23919\/DATE.2017.7927203"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Frank, E., Hall, M., Holmes, G., Kirkby, R., Pfahringer, B., Witten, I.H., and Trigg, L. (2009). Weka\u2014A machine learning workbench for data mining. Data Mining and Knowledge Discovery Handbook, Springer.","DOI":"10.1007\/978-0-387-09823-4_66"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"10549","DOI":"10.1007\/s10586-017-1109-8","article-title":"An enhanced J48 classification algorithm for the anomaly intrusion detection systems","volume":"22","author":"Aljawarneh","year":"2019","journal-title":"Clust. Comput."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"Binkert","year":"2011","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"ref_23","unstructured":"Bienia, C., and Li, K. (2011). Benchmarking Modern Multiprocessors, Princeton University."},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Woo, S.C., Ohara, M., Torrie, E., Singh, J.P., and Gupta, A. (1995, January 22\u201324). The SPLASH-2 programs: Characterization and methodological considerations. Proceedings of the 22nd Annual International Symposium on Computer Architecture, S. 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