{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T02:11:50Z","timestamp":1760235110281,"version":"build-2065373602"},"reference-count":27,"publisher":"MDPI AG","issue":"8","license":[{"start":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T00:00:00Z","timestamp":1626825600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Algorithms"],"abstract":"<jats:p>Open-source processors are increasingly being adopted by the industry, which requires all sorts of open-source implementations of peripherals and other system-on-chip modules. Despite the recent advent of open-source hardware, the available open-source caches have low configurability, limited lack of support for single-cycle pipelined memory accesses, and use non-standard hardware interfaces. In this paper, the IObundle cache (IOb-Cache), a high-performance configurable open-source cache is proposed, developed and deployed. The cache has front-end and back-end modules for fast integration with processors and memory controllers. The front-end module supports the native interface, and the back-end module supports the native interface and the standard Advanced eXtensible Interface (AXI). The cache is highly configurable in structure and access policies. The back-end can be configured to read bursts of multiple words per transfer to take advantage of the available memory bandwidth. To the best of our knowledge, IOb-Cache is currently the only configurable cache that supports pipelined Central Processing Unit (CPU) interfaces and AXI memory bus interface. Additionally, it has a write-through buffer and an independent controller for fast, most of the time 1-cycle writing together with 1-cycle reading, while previous works only support 1-cycle reading. This allows the best clocks-per-Instruction (CPI) to be close to one (1.055). IOb-Cache is integrated into IOb System-on-Chip (IOb-SoC) Github repository, which has 29 stars and is already being used in 50 projects (forks).<\/jats:p>","DOI":"10.3390\/a14080218","type":"journal-article","created":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T11:53:23Z","timestamp":1626868403000},"page":"218","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["IOb-Cache: A High-Performance Configurable Open-Source Cache"],"prefix":"10.3390","volume":"14","author":[{"given":"Jo\u00e3o V.","family":"Roque","sequence":"first","affiliation":[{"name":"IObundle, Lda., 1000-158 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8903-9715","authenticated-orcid":false,"given":"Jo\u00e3o D.","family":"Lopes","sequence":"additional","affiliation":[{"name":"INESC-ID, 1000-029 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8556-4507","authenticated-orcid":false,"given":"M\u00e1rio P.","family":"V\u00e9stias","sequence":"additional","affiliation":[{"name":"INESC-ID, 1000-029 Lisbon, Portugal"},{"name":"Instituto Superior de Engenharia de Lisboa, 1959-007 Lisbon, Portugal"},{"name":"Instituto Polit\u00e9cnico de Lisboa, 1549-003 Lisbon, Portugal"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7525-7546","authenticated-orcid":false,"given":"Jos\u00e9 T.","family":"de Sousa","sequence":"additional","affiliation":[{"name":"INESC-ID, 1000-029 Lisbon, Portugal"},{"name":"Instituto Superior T\u00e9cnico, Universidade de Lisboa, 1649-004 Lisbon, Portugal"}]}],"member":"1968","published-online":{"date-parts":[[2021,7,21]]},"reference":[{"key":"ref_1","unstructured":"Akula, R., Jain, K., and Kotecha, D.J. (2019). System Performance with varying L1 Instruction and Data Cache Sizes: An Empirical Analysis. arXiv."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Ullah, Z., Minallah, N., Marwat, S.N.K., Hafeez, A., and Fouzder, T. (2019, January 26\u201328). Performance Analysis of Cache Size and Set-Associativity using simpleScalar Benchmark. Proceedings of the 2019 5th International Conference on Advances in Electrical Engineering (ICAEE), Dhaka, Bangladesh.","DOI":"10.1109\/ICAEE48663.2019.8975563"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Das, V.V., Thomas, G., and Lumban Gaol, F. (2011). Understanding the Impact of Cache Performance on Multi-core Architectures. Information Technology and Mobile Communication, Springer.","DOI":"10.1007\/978-3-642-20573-6"},{"key":"ref_4","unstructured":"Ramasubramanian, N., Srinivas, V., and Ammasai Gounden, N. (2011). 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Study of Different Cache Line Replacement Algorithms in Embedded Systems. [Master\u2019s Thesis, KHT\u2014Royal Institute of Technology in Stockholm]."}],"container-title":["Algorithms"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1999-4893\/14\/8\/218\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T06:32:43Z","timestamp":1760164363000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1999-4893\/14\/8\/218"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7,21]]},"references-count":27,"journal-issue":{"issue":"8","published-online":{"date-parts":[[2021,8]]}},"alternative-id":["a14080218"],"URL":"https:\/\/doi.org\/10.3390\/a14080218","relation":{},"ISSN":["1999-4893"],"issn-type":[{"type":"electronic","value":"1999-4893"}],"subject":[],"published":{"date-parts":[[2021,7,21]]}}}