{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,15]],"date-time":"2026-06-15T14:35:30Z","timestamp":1781534130470,"version":"3.54.5"},"reference-count":20,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2026,4,3]],"date-time":"2026-04-03T00:00:00Z","timestamp":1775174400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003392","name":"Natural Science Foundation of Fujian Province","doi-asserted-by":"publisher","award":["2024J01363"],"award-info":[{"award-number":["2024J01363"]}],"id":[{"id":"10.13039\/501100003392","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Young and Middle-aged Teachers Education and Research Project of Fujian Province","award":["JZ230001"],"award-info":[{"award-number":["JZ230001"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"award":["92373207"],"award-info":[{"award-number":["92373207"]}],"id":[{"id":"https:\/\/ror.org\/01h0zpd94","id-type":"ROR","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Algorithms"],"abstract":"<jats:p>Logic synthesis is a critical stage in the VLSI design flow. Logic synthesis methods without considering physical information would result in inferior solutions with timing violations and fail to meet high-performance design requirements. In this paper, we present an analytical placement algorithm that generates timing-friendly physical information to promote high-performance logic synthesis solutions. To address the crucial congestion issue, we first propose a fence-region-aware density model. Then, a boundary-based quadratic penalty model is constructed to ensure the cells do not violate the legal boundaries. Finally, we develop a Polak\u2013Ribi\u00e8re-based placement algorithm to guide the cell movement while optimizing circuit timing. Compared to the advanced placement work, the experimental results on industrial benchmarks show that our proposed algorithm achieves 7% WNS improvement and 12% TNS optimization with 3% better logic depth.<\/jats:p>","DOI":"10.3390\/a19040280","type":"journal-article","created":{"date-parts":[[2026,4,6]],"date-time":"2026-04-06T02:06:21Z","timestamp":1775441181000},"page":"280","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["High-Performance Placement for VLSI Logic Synthesis"],"prefix":"10.3390","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0009-0005-5881-2604","authenticated-orcid":false,"given":"Zhifeng","family":"Lin","sequence":"first","affiliation":[{"name":"Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou 350108, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuhao","family":"Jiang","sequence":"additional","affiliation":[{"name":"Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou 350108, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zuodong","family":"Liu","sequence":"additional","affiliation":[{"name":"Shanghai LEDA Technology Co., Ltd., Shanghai 201203, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jiarui","family":"Chen","sequence":"additional","affiliation":[{"name":"College of Computer and Data Science, Fuzhou University, Fuzhou 350108, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2026,4,3]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"696","DOI":"10.1109\/TCAD.2024.3436521","article-title":"DG-RePlAce: A Dataflow-Driven GPU-Accelerated Analytical Global Placement Framework for Machine Learning Accelerators","volume":"44","author":"Kahng","year":"2025","journal-title":"IEEE Trans. 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