{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T01:42:49Z","timestamp":1760060569694,"version":"build-2065373602"},"reference-count":30,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T00:00:00Z","timestamp":1757548800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computation"],"abstract":"<jats:p>Calculations testing can be effectively used in the construction of discrete self-checking devices. Calculations testing is based on the parity and self-duality of the calculated functions. This can be used for modern blocks and nodes of control systems for responsible technological processes. However, its use has a number of features that must be considered when building concurrent error-detection circuits. The authors used methods of discrete mathematics and Boolean algebra as well as technical diagnostics of discrete systems to investigate the problem of ensuring the testability of the parity encoder. Theorems on the testability of convolution functions modulo 2 are proved. Considering these theorems allowed the authors of the article to propose a method for synthesizing CED circuits. This method increases the testability of the encoder for parity. This method is based on the use of two diagnostic signs at once. The first sign is that the code words belong to the parity code. The second is the self-dual control function in the concurrent error-detection circuit. This method is guaranteed to increase the testability of the parity coder compared to using one of the diagnostic signs for calculations testing. Experiments with testing discrete devices have shown the effectiveness of the organization structure of the concurrent error-detection circuit that we developed. The theorems that we proved form the basis of proof of similar provisions for the use of other linear codes in the synthesis of concurrent error-detection circuits. Our proposed solutions with calculations testing based on two diagnostic signs should be used in the synthesis of discrete systems. Discrete systems should be self-checking and have improved testability indicators.<\/jats:p>","DOI":"10.3390\/computation13090220","type":"journal-article","created":{"date-parts":[[2025,9,11]],"date-time":"2025-09-11T08:55:02Z","timestamp":1757580902000},"page":"220","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["A Method for Synthesizing Self-Checking Discrete Systems with Calculations Testing Based on Parity and Self-Duality of Calculated Functions"],"prefix":"10.3390","volume":"13","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4563-6411","authenticated-orcid":false,"given":"Dmitry V.","family":"Efanov","sequence":"first","affiliation":[{"name":"Higher School of Cyberphysical Systems & Control, Institute of Cybersecurity and Computer Science, Peter the Great St. Petersburg Polytechnic University, 195251 St. Petersburg, Russia"},{"name":"Higher School of Transport, Institute of Machinery, Materials and Transport, Peter the Great St. Petersburg Polytechnic University, 195251 St. Petersburg, Russia"},{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"},{"name":"Automation, Remote Control and Communication on Railway Transport Department, Russian University of Transport, 127994 Moscow, Russia"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9171-234X","authenticated-orcid":false,"given":"Tatiana S.","family":"Pogodina","sequence":"additional","affiliation":[{"name":"Higher School of Transport, Institute of Machinery, Materials and Transport, Peter the Great St. Petersburg Polytechnic University, 195251 St. Petersburg, Russia"}]},{"given":"Nazirjan M.","family":"Aripov","sequence":"additional","affiliation":[{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"}]},{"given":"Sunnatillo T.","family":"Boltayev","sequence":"additional","affiliation":[{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"}]},{"given":"Asadulla R.","family":"Azizov","sequence":"additional","affiliation":[{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"}]},{"given":"Elnara K.","family":"Ametova","sequence":"additional","affiliation":[{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"}]},{"given":"Zohid B.","family":"Toshboyev","sequence":"additional","affiliation":[{"name":"Automation and Remote Control Department, Tashkent State Transport University, Tashkent 100167, Uzbekistan"}]}],"member":"1968","published-online":{"date-parts":[[2025,9,11]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Drozd, O., Perebeinos, I., Martynyuk, O., Zashcholkin, K., Ivanova, O., and Drozd, M. (2020, January 25\u201329). Hidden Fault Analysis of FPGA Projects for Critical Applications. Proceedings of the IEEE International Conference on Advanced Trends in Radioelectronics, Telecommunications and Computer Engineering (TCSET), Lviv-Slavsko, Ukraine.","DOI":"10.1109\/TCSET49122.2020.235591"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Chioktour, V., and Kakarountas, A. (2022). Adaptive BIST for Concurrent On-Line Testing on Combinational Circuits. Electronics, 19.","DOI":"10.3390\/electronics11193193"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Soltani, S., and Kouhanjani, M.J. (2023, January 8\u20139). Comparing Three Separate Discrete Algorithms for Generation Maintenance Optimization. Proceedings of the 8th International Conference on Technology and Energy Management (ICTEM), Babol, Iran.","DOI":"10.1109\/ICTEM56862.2023.10084330"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"293","DOI":"10.11591\/ijra.v13i3.pp293-306","article-title":"Vector Synthesis of Fault Testing Map for Logic","volume":"13","author":"Hahanov","year":"2024","journal-title":"IAES Int. J. Robot. Autom. (IJRA)"},{"key":"ref_5","unstructured":"Mitra, S., and McCluskey, E.J. (2000, January 3\u20135). Which Concurrent Error Detection Scheme to Choose?. Proceedings of the International Test Conference, Atlantic City, NJ, USA."},{"key":"ref_6","unstructured":"Sahana, A.R., Chiraag, V., Suresh, G., Thejaswini, P., and Nandi, S. (2023, January 23\u201325). Application of Error Detection and Correction Techniques to Self-Checking VLSI Systems: An Overview. Proceedings of the 2023 IEEE Guwahati Subsection Conference (GCON), Guwahati, India."},{"key":"ref_7","first-page":"1085","article-title":"Methods for Providing Safety in Discrete Systems","volume":"55","author":"Gavzov","year":"1994","journal-title":"Autom. Remote Control"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Dobias, R., Konarski, J., and Kubatova, H. (2008, January 3\u20135). Dependability Evaluation of Real Railway Interlocking Device. Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, Parma, Italy.","DOI":"10.1109\/DSD.2008.122"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"531","DOI":"10.3103\/S1068371220090035","article-title":"Methods of Providing Hardware Safety for Microprocessor Train Control Systems","volume":"91","author":"Bestemyanov","year":"2020","journal-title":"Russ. Electr. Eng."},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Falkowski, K., \u017bokowski, M., Chodnicki, M., Mazur, M., and Wito\u015b, M. (2019, January 26\u201327). Self-Diagnostic System for Mini UAV. Proceedings of the New Trends in Aviation Development (NTAD), Chlumec nad Cidlinou, Czech Republic.","DOI":"10.1109\/NTAD.2019.8875542"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"32729","DOI":"10.1109\/JSEN.2024.3450859","article-title":"A Hybrid Multimodel-Based Condition Monitoring and Sensor Fault Detection Method for Aero Gas Turbine","volume":"24","author":"Chen","year":"2024","journal-title":"IEEE Sens. J."},{"key":"ref_12","unstructured":"Sogomonian, E.S., and Slabakov, E.V. (1989). Self-Checking Devices and Fault-Tolerant Systems, Radio and Communications. (In Russian)."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Drozd, A., Kharchenko, V., Antoshchuk, S., Sulima, J., and Drozd, M. (2011, January 9\u201312). Checkability of the Digital Components in Safety-Critical Systems: Problems and Solutions. Proceedings of the 9th IEEE East-West Design & Test Symposium (EWDTS\u20192011), Sevastopol, Ukraine.","DOI":"10.1109\/EWDTS.2011.6116606"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Efanov, D., Sapozhnikov, V., and Sapozhnikov, V.I. (October, January 29). Generalized Algorithm of Building Summation Codes for the Tasks of Technical Diagnostics of Discrete Systems. Proceedings of the 15th IEEE East-West Design & Test Symposium (EWDTS\u20192017), Novi Sad, Serbia.","DOI":"10.1109\/EWDTS.2017.8110126"},{"key":"ref_15","unstructured":"G\u00f6essel, M., Ocheretny, V., Sogomonyan, E., and Marienfeld, D. (2008). New Methods of Concurrent Checking, Springer Science + Business Media B.V.. [1st ed.]."},{"key":"ref_16","unstructured":"Saposhnikov, V., Dmitriev, A., Goessel, M., and Saposhnikov, V.V. (May, January 28). Self-Dual Parity Checking\u2014A New Method for on Line Testing. Proceedings of the 14th IEEE VLSI Test Symposium, Princeton, NJ, USA."},{"key":"ref_17","first-page":"1653","article-title":"A Functional Fault-Detection Self-Test for Combinational Circuits","volume":"60","author":"Goessel","year":"1999","journal-title":"Autom. Remote Control"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1155\/2000\/84720","article-title":"New Self-Dual Circuits for Error Detection and Testing","volume":"11","author":"Dmitriev","year":"2000","journal-title":"VLSI Des."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Crama, Y., and Hammer, P.L. (2011). Boolean Functions: Theory, Algorithms, and Applications, Cambridge University Press.","DOI":"10.1017\/CBO9780511852008"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Efanov, D.V., Pivovarov, D.V., Cortegoso Vissio, N., Kuptsov, A.O., and Egorov, D.E. (2025). Method for Testing Combinational Circuits by Multiple Diagnostic Features Using Weight-Based Sum Codes Properties. Automation, 6.","DOI":"10.3390\/automation6010006"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"267","DOI":"10.1007\/BF00971975","article-title":"Design of Self-Testing and On-Line Fault Detection Combinational Circuits with Weakly Independent Outputs","volume":"4","author":"Sogomonyan","year":"1993","journal-title":"J. Electron. Test. Theory Appl."},{"key":"ref_22","unstructured":"Lala, P.K. (2001). Self-Checking and Fault-Tolerant Digital Design, Morgan Kaufmann Publishers."},{"key":"ref_23","unstructured":"Zakrevskij, A., Pottosin, Y., and Cheremisinova, L. (2009). Optimization in Boolean Space, TUT Press."},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Efanov, D.V., Pogodina, T.S., Aripov, N.M., Boltayev, S.T., Azizov, A.R., Ametova, E.K., and Shakirova, F.F. (2025). Combinational Circuits Testing Based on Hsiao Codes with Self-Dual Check Functions. Computation, 13.","DOI":"10.3390\/computation13010015"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Efanov, D.V., and Pogodina, T.S. (2024, January 13\u201317). Hamming Codes with Check Bits that are Described by Self-Dual and Self-Quasidual Boolean Functions. Proceedings of the 20th IEEE East-West Design & Test Symposium (EWDTS\u20192024), Yerevan, Armenia.","DOI":"10.1109\/EWDTS63723.2024.10873722"},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Higami, Y., Takahashi, H., Kobayashi, S.-Y., and Saluja, K.K. (2014, January 9\u201311). Diagnosis of Gate Delay Faults in the Presence of Clock Delay Faults. Proceedings of the IEEE Computer Society Annual Symposium on VLSI, Tampa, FL, USA.","DOI":"10.1109\/ISVLSI.2014.60"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"1949","DOI":"10.1134\/S0005117921110102","article-title":"Constructing a Sequence Detecting Robustly Testable Path Delay Faults in Sequential Circuits","volume":"82","author":"Matrosova","year":"2021","journal-title":"Autom. Remote Control"},{"key":"ref_28","first-page":"1192","article-title":"Detection of Faults in Combinational Circuits by a Self-Dual Test","volume":"61","author":"Goessel","year":"2000","journal-title":"Autom. Remote Control"},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"953","DOI":"10.14716\/ijtech.v10i5.1144","article-title":"A New Method for Building Low-Density-Parity-Check Codes","volume":"10","author":"Amine","year":"2019","journal-title":"Int. J. Technol."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"2143","DOI":"10.1109\/TC.2015.2479617","article-title":"Multiple-Bit Parity-Based Concurrent Fault Detection Architecture for Parallel CRC Computation","volume":"65","author":"Gangopadhyay","year":"2016","journal-title":"IEEE Trans. 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