{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,20]],"date-time":"2026-03-20T20:47:14Z","timestamp":1774039634360,"version":"3.50.1"},"reference-count":39,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2021,1,27]],"date-time":"2021-01-27T00:00:00Z","timestamp":1611705600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers"],"abstract":"<jats:p>Decimal arithmetic using software is slow for very large-scale applications. On the other hand, when hardware is employed, extra area overhead is required. A balanced strategy can overcome both issues. Our proposed methods are compliant with the IEEE 754-2008 standard for decimal floating-point arithmetic and combinations of software and hardware. In our methods, software with some area-efficient decimal component (hardware) is used to design the multiplication process. Analysis in a RISC-V-based integrated co-design evaluation framework reveals that the proposed methods provide several Pareto points for decimal multiplication solutions. The total execution process is sped up by 1.43\u00d7 to 2.37\u00d7 compared with a full software solution. In addition, 7\u201397% less hardware is required compared with an area-efficient full hardware solution.<\/jats:p>","DOI":"10.3390\/computers10020017","type":"journal-article","created":{"date-parts":[[2021,1,27]],"date-time":"2021-01-27T06:10:54Z","timestamp":1611727854000},"page":"17","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Hardware\u2013Software Co-Design for Decimal Multiplication"],"prefix":"10.3390","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6550-5753","authenticated-orcid":false,"given":"Riaz-ul-haque","family":"Mian","sequence":"first","affiliation":[{"name":"Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma 630-0192, Japan"}]},{"given":"Michihiro","family":"Shintani","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma 630-0192, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9837-5147","authenticated-orcid":false,"given":"Michiko","family":"Inoue","sequence":"additional","affiliation":[{"name":"Graduate School of Science and Technology, Nara Institute of Science and Technology, Ikoma 630-0192, Japan"}]}],"member":"1968","published-online":{"date-parts":[[2021,1,27]]},"reference":[{"key":"ref_1","unstructured":"Cowlishaw, M.F. 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