{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,26]],"date-time":"2025-12-26T03:30:12Z","timestamp":1766719812850,"version":"build-2065373602"},"reference-count":14,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2025,4,11]],"date-time":"2025-04-11T00:00:00Z","timestamp":1744329600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["2119485"],"award-info":[{"award-number":["2119485"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers"],"abstract":"<jats:p>The rise of 3D heterogeneous packaging holds promise for increased performance in applications such as AI by bringing compute and memory modules into close proximity. This increased performance comes with increased thermal management challenges. This research explores the use of thermal sensing and load throttling combined with federated computation to manage localized internal heating in a multi-3D chip package. The overall concept is that individual chiplets may heat at different rates due to operational and geometric factors. Shifting computational loads from hot to cooler chiplets can prevent local overheating while maintaining overall computational output. This concept is verified with experiments in a low-cost test vehicle. The test vehicle mimics a 3D chiplet stack with a tightly stacked assembly of SoC devices. These devices can sense and report internal temperature and dynamically adjust frequency. The configuration is for ESP32-S3 microcontrollers to work on a federated computational task, while reporting internal temperature to a host controller. The tight packing of processors causes temperatures to rise, with those internal to the stack rising more quickly than external ones. With real-time temperature monitoring, when the temperatures exceed a threshold, the AI system reduces the processor frequency, i.e., throttles the processor, to save power and dynamically shifts part of the workload to other ESP32-S3s with lower temperatures. This approach maximizes overall efficiency while maintaining thermal safety without compromising computational power. Experimental results with up to six processors confirm the validity of the concept.<\/jats:p>","DOI":"10.3390\/computers14040147","type":"journal-article","created":{"date-parts":[[2025,4,14]],"date-time":"2025-04-14T03:39:16Z","timestamp":1744601956000},"page":"147","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["An Approach to Thermal Management and Performance Throttling for Federated Computation on a Low-Cost 3D ESP32-S3 Package Stack"],"prefix":"10.3390","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-3453-4185","authenticated-orcid":false,"given":"Yi","family":"Liu","sequence":"first","affiliation":[{"name":"Department of Mechanical Engineering, University of Vermont, Burlington, VT 05405, USA"}]},{"given":"Parth Sandeepbhai","family":"Shah","sequence":"additional","affiliation":[{"name":"Intel Corporation, Chandler, AZ 85224, USA"}]},{"given":"Tian","family":"Xia","sequence":"additional","affiliation":[{"name":"Department of Computer Science, University of Vermont, Burlington, VT 05405, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0957-0574","authenticated-orcid":false,"given":"Dryver","family":"Huston","sequence":"additional","affiliation":[{"name":"Department of Mechanical Engineering, University of Vermont, Burlington, VT 05405, USA"}]}],"member":"1968","published-online":{"date-parts":[[2025,4,11]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"8","DOI":"10.1108\/13565361111127304","article-title":"Overview and outlook of through-silicon via (TSV) and 3D integrations","volume":"28","author":"Lau","year":"2011","journal-title":"Microelectron. Int."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Shaikh, S.F. (2020). Heterogeneous Integration Strategy for Obtaining Physically Flexible 3d Compliant Electronic Systems. [Ph.D. Dissertation, King Abdullah University of Science and Technology].","DOI":"10.1109\/ECTC32696.2021.00344"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"6044","DOI":"10.1039\/D4NA00578C","article-title":"Challenges and Opportunities in Engineering of Next Generation 3D Microelectronic Devices: Improved Performance, Higher Integration Density","volume":"6","author":"Singh","year":"2024","journal-title":"Nanoscale Adv."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"5598","DOI":"10.1109\/TED.2021.3111857","article-title":"Heterogeneous 3-d integration of multitier compute-in-memory accelerators: An electrical-thermal co-design","volume":"68","author":"Peng","year":"2021","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1442","DOI":"10.1016\/j.fmre.2024.04.004","article-title":"The Application of Multi-scale Simulation in Advanced Electronic Packaging","volume":"4","author":"Yu","year":"2024","journal-title":"Fundam. Res."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"105005","DOI":"10.1088\/1361-6439\/ab9f00","article-title":"Ti\/Si interface enabling complementary metal oxide semiconductor compatible, high reliable bonding for inter-die micro-fluidic cooling for future advanced 3D integrated circuit integration","volume":"30","author":"Cheemalamarri","year":"2020","journal-title":"J. Micromech. Microeng."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Chang, Y.W. (2024, January 12\u201315). Physical Design Challenges in Modern Heterogeneous Integration. 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Res."}],"container-title":["Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-431X\/14\/4\/147\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,9]],"date-time":"2025-10-09T17:13:08Z","timestamp":1760029988000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-431X\/14\/4\/147"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4,11]]},"references-count":14,"journal-issue":{"issue":"4","published-online":{"date-parts":[[2025,4]]}},"alternative-id":["computers14040147"],"URL":"https:\/\/doi.org\/10.3390\/computers14040147","relation":{},"ISSN":["2073-431X"],"issn-type":[{"type":"electronic","value":"2073-431X"}],"subject":[],"published":{"date-parts":[[2025,4,11]]}}}