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The method allows emulating standard 32 bit floating point multipliers using a chain of fixed point adders and a logic unit to manage the exponent, in order to obtain IEEE-754 compliant results. The proposed design allows more compact implementation of a floating point filtering architecture when a fixed set of coefficients and a fixed range of input values are used. The elaboration of the data proceeds in raster-scan order and is capable of directly processing the data coming from the acquisition source thanks to a careful organization of the memories, avoiding the implementation of frame buffers or any aligning circuitry. The proposed architecture shows state-of-the-art performances in terms of critical path delay, obtaining a critical path delay of 4.7 ns when implemented on a Xilinx Virtex 7 FPGA board.<\/jats:p>","DOI":"10.3390\/computers6020019","type":"journal-article","created":{"date-parts":[[2017,5,17]],"date-time":"2017-05-17T11:13:17Z","timestamp":1495019597000},"page":"19","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Design of a Convolutional Two-Dimensional Filter in FPGA for Image Processing Applications"],"prefix":"10.3390","volume":"6","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1913-4928","authenticated-orcid":false,"given":"Gian","family":"Licciardo","sequence":"first","affiliation":[{"name":"Department of Industrial Engineering, University of Salerno, 84084 Fisciano (SA), Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5798-378X","authenticated-orcid":false,"given":"Carmine","family":"Cappetta","sequence":"additional","affiliation":[{"name":"Department of Industrial Engineering, University of Salerno, 84084 Fisciano (SA), Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Luigi","family":"Di Benedetto","sequence":"additional","affiliation":[{"name":"Department of Industrial Engineering, University of Salerno, 84084 Fisciano (SA), Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2017,5,17]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1510","DOI":"10.1109\/TCSVT.2013.2248492","article-title":"VLSI implementation of an adaptive edge-enhanced image scalar for real-time multimedia applications","volume":"23","author":"Chen","year":"2013","journal-title":"IEEE Trans. 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