{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:17:00Z","timestamp":1760242620976,"version":"build-2065373602"},"reference-count":40,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2017,12,22]],"date-time":"2017-12-22T00:00:00Z","timestamp":1513900800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers"],"abstract":"<jats:p>Embedded systems have stringent design constraints, which has necessitated much prior research focus on optimizing energy consumption and\/or performance. Since embedded systems typically have fewer cooling options, rising temperature, and thus temperature optimization, is an emergent concern. Most embedded systems only dissipate heat by passive convection, due to the absence of dedicated thermal management hardware mechanisms. The embedded system\u2019s temperature not only affects the system\u2019s reliability, but can also affect the performance, power, and cost. Thus, embedded systems require efficient thermal management techniques. However, thermal management can conflict with other optimization objectives, such as execution time and energy consumption. In this paper, we focus on managing the temperature using a synergy of cache optimization and dynamic frequency scaling, while also optimizing the execution time and energy consumption. This paper provides new insights on the impact of cache parameters on efficient temperature-aware cache tuning heuristics. In addition, we present temperature-aware phase-based tuning, TaPT, which determines Pareto optimal clock frequency and cache configurations for fine-grained execution time, energy, and temperature tradeoffs. TaPT enables autonomous system optimization and also allows designers to specify temperature constraints and optimization priorities. Experiments show that TaPT can effectively reduce execution time, energy, and temperature, while imposing minimal hardware overhead.<\/jats:p>","DOI":"10.3390\/computers7010003","type":"journal-article","created":{"date-parts":[[2017,12,22]],"date-time":"2017-12-22T05:50:19Z","timestamp":1513921819000},"page":"3","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["TaPT: Temperature-Aware Dynamic Cache Optimization for Embedded Systems"],"prefix":"10.3390","volume":"7","author":[{"given":"Tosiron","family":"Adegbija","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Arizona, Tucson, AZ 85721, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ann","family":"Gordon-Ross","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL 32611, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2017,12,22]]},"reference":[{"key":"ref_1","unstructured":"Brooks, D., and Martonosi, M. (2001, January 19\u201324). Dynamic thermal management for high-performance microprocessors. Proceedings of the Seventh International Symposium on IEEE High-Performance Computer Architecture (HPCA), Monterrey, Nuevo Leon, Mexico."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"94","DOI":"10.1145\/980152.980157","article-title":"Temperature-aware microarchitecture: Modeling and implementation","volume":"1","author":"Skadron","year":"2004","journal-title":"ACM Trans. Archit. Code Optim. (TACO)"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Heo, S., Barr, K., and Asanovi\u0107, K. (2003, January 25\u201327). Reducing power density through activity migration. Proceedings of the 2003 International Symposium on Low Power Electronics and Design, Seoul, Korea.","DOI":"10.1145\/871506.871561"},{"key":"ref_4","unstructured":"(2016, December 21). ARM. Available online: http:\/\/www.arm.com."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1487","DOI":"10.1109\/JPROC.2006.879797","article-title":"Thermal modeling, analysis, and management in VLSI circuits: Principles and methods","volume":"94","author":"Pedram","year":"2006","journal-title":"Proc. IEEE"},{"key":"ref_6","unstructured":"Yeo, I., and Kim, E.J. (2009, January 20\u201324). Temperature-aware scheduler based on thermal behavior grouping in multicore systems. Proceedings of the Conference on Design, Automation and Test in Europe, Nice, France."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Jayaseelan, R., and Mitra, T. (2008, January 10\u201313). Temperature aware task sequencing and voltage scaling. Proceedings of the 2008 IEEE\/ACM International Conference on Computer-Aided Design, San Jose, CA, USA.","DOI":"10.1109\/ICCAD.2008.4681641"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Gordon-Ross, A., Lau, J., and Calder, B. (2008, January 4\u20136). Phase-based cache reconfiguration for a highly-configurable two-level cache hierarchy. Proceedings of the 18th ACM Great Lakes Symposium on VLSI, Orlando, FL, USA.","DOI":"10.1145\/1366110.1366200"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1109\/TVLSI.2008.2002459","article-title":"Fast configurable-cache tuning with a unified second-level cache","volume":"17","author":"Vahid","year":"2009","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"163","DOI":"10.1007\/s12667-013-0090-4","article-title":"Optimizing cache energy efficiency in multicore power system simulations","volume":"5","author":"Khaitan","year":"2014","journal-title":"Energy Syst."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Zhang, C., Vahid, F., and Najjar, W. (2003, January 9\u201311). A highly configurable cache architecture for embedded systems. Proceedings of the IEEE 30th Annual International Symposium on Computer Architecture, San Diego, CA, USA.","DOI":"10.1145\/859634.859635"},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Homayoun, H., Rahmatian, M., Kontorinis, V., Golshan, S., and Tullsen, D.M. (2012, January 19\u201321). Hot peripheral thermal management to mitigate cache temperature variation. Proceedings of the IEEE Thirteenth International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA.","DOI":"10.1109\/ISQED.2012.6187576"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"1012","DOI":"10.1109\/TVLSI.2016.2606579","article-title":"Bias Temperature Instability Mitigation via Adaptive Cache Size Management","volume":"25","author":"Rohbani","year":"2017","journal-title":"IEEE Trans. Very Large Scale Integr. (VLSI) Syst."},{"key":"ref_14","unstructured":"Zitzler, E., Laumanns, M., and Thiele, L. (2001). SPEA2: Improving the Strength Pareto Evolutionary Algorithm, Eurogen."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Adegbija, T., Gordon-Ross, A., and Rawlins, M. (2014, January 5\u20137). Analysis of cache tuner architectural layouts for multicore embedded systems. Proceedings of the IEEE International Performance Computing and Communications Conference (IPCCC), Austin, TX, USA.","DOI":"10.1109\/PCCC.2014.7017091"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Hajimiri, H., and Mishra, P. (2012, January 7\u201311). Intra-task dynamic cache reconfiguration. Proceedings of the IEEE 25th International Conference on VLSI Design (VLSID), Hyderabad, India.","DOI":"10.1109\/VLSID.2012.109"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"1068","DOI":"10.1007\/s11227-014-1140-y","article-title":"Proactive task migration with a self-adjusting migration threshold for dynamic thermal management of multi-core processors","volume":"68","author":"Salami","year":"2014","journal-title":"J. Supercomput."},{"key":"ref_18","unstructured":"Sherwood, T., and Calder, B. (1999). Time Varying Behavior of Programs, UCSD. UCSD Technical Report CS99-630."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Balasubramonian, R., Albonesi, D., Buyuktosunoglu, A., and Dwarkadas, S. (2000, January 10\u201313). Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures. Proceedings of the 33rd Annual ACM\/IEEE International Symposium on Microarchitecture, Monterey, CA, USA.","DOI":"10.1145\/360128.360153"},{"key":"ref_20","unstructured":"Dhodapkar, A.S., and Smith, J.E. (2003, January 3\u20135). Comparing program phase detection techniques. Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, San Diego, CA, USA."},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Sembrant, A., Eklov, D., and Hagersten, E. (2011, January 6\u20138). Efficient software-based online phase classification. Proceedings of the 2011 IEEE International Symposium on Workload Characterization (IISWC), Austin, TX, USA.","DOI":"10.1109\/IISWC.2011.6114207"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Huang, W., Stan, M.R., Skadron, K., Sankaranarayanan, K., Ghosh, S., and Velusam, S. (2004, January 7\u201311). Compact thermal modeling for temperature-aware design. Proceedings of the 41st Annual Design Automation Conference, San Diego, CA, USA.","DOI":"10.1145\/996566.996800"},{"key":"ref_23","unstructured":"Liu, Z., Xu, T., Tan, S.X.D., and Wang, H. (2013, January 22\u201325). Dynamic thermal management for multi-core microprocessors considering transient thermal effects. Proceedings of the IEEE 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan."},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1145\/2187671.2187675","article-title":"Recent thermal management techniques for microprocessors","volume":"44","author":"Kong","year":"2012","journal-title":"ACM Comput. Surv. (CSUR)"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Malik, A., Moyer, B., and Cermak, D. (2000, January 26\u201327). A low power unified cache architecture providing power and performance flexibility. Proceedings of the IEEE 2000 International Symposium on Low Power Electronics and Design (ISLPED), Rapallo, Italy.","DOI":"10.1145\/344166.344610"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"46","DOI":"10.1145\/1577129.1577137","article-title":"Real time power estimation and thread scheduling via performance counters","volume":"37","author":"Singh","year":"2009","journal-title":"ACM SIGARCH Comput. Archit. News"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"881","DOI":"10.1109\/TPAMI.2002.1017616","article-title":"An efficient k-means clustering algorithm: Analysis and implementation","volume":"24","author":"Kanungo","year":"2002","journal-title":"IEEE Trans. Pattern Anal. Mach. Intell."},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Herbert, S., and Marculescu, D. (2009, January 14\u201318). Variation-aware dynamic voltage\/frequency scaling. Proceedings of the IEEE 15th International Symposium on High Performance Computer Architecture (HPCA), Raleigh, NC, USA.","DOI":"10.1109\/HPCA.2009.4798265"},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"251","DOI":"10.1007\/s10617-014-9127-8","article-title":"Phase distance mapping: A phase-based cache tuning methodology for embedded systems","volume":"18","author":"Adegbija","year":"2014","journal-title":"Des. Autom. Embed. Syst."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"336","DOI":"10.1145\/871656.859657","article-title":"Phase tracking and prediction","volume":"Volume 31","author":"Sherwood","year":"2003","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"ref_31","unstructured":"(2017, January 21). Design Compiler. Available online: https:\/\/www.synopsys.com\/."},{"key":"ref_32","unstructured":"(2017, April 21). MIPS32 M14K Processor Core Family. Available online: https:\/\/imagination-technologies-cloudfront-assets.s3.amazonaws.com\/documentation\/MD00668-2B-M14K-SUM-02.04.pdf."},{"key":"ref_33","first-page":"1","article-title":"The gem5 Simulator","volume":"40","author":"Binkert","year":"2012","journal-title":"Comput. Archit. News"},{"key":"ref_34","first-page":"5","article-title":"The mcpat framework for multicore and manycore architectures: Simultaneously modeling power, area, and timing","volume":"10","author":"Li","year":"2013","journal-title":"ACM Trans. Archit. Code Optim. (TACO)"},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Sharifi, S., Coskun, A.K., and Rosing, T.S. (2010, January 18\u201321). Hybrid dynamic energy and thermal management in heterogeneous embedded multiprocessor SoCs. Proceedings of the 2010 Asia and South Pacific Design Automation Conference, Taipei, Taiwan.","DOI":"10.1109\/ASPDAC.2010.5419681"},{"key":"ref_36","unstructured":"(2017, January 21). The Embedded Microprocessor Benchmark Consortium. Available online: http:\/\/www.eembc.org\/."},{"key":"ref_37","unstructured":"Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., and Brown, R.B. (2001, January 2). MiBench: A free, commercially representative embedded benchmark suite. Proceedings of the IEEE International Workshop on Workload Characterization (WWC), Austin, TX, USA."},{"key":"ref_38","doi-asserted-by":"crossref","unstructured":"Gordon-Ross, A., and Vahid, F. (2007, January 4\u20138). A self-tuning configurable cache. Proceedings of the 44th annual Design Automation Conference, San Diego, CA, USA.","DOI":"10.1109\/DAC.2007.375159"},{"key":"ref_39","unstructured":"Rawlins, M., and Gordon-Ross, A. (February, January 30). An application classification guided cache tuning heuristic for multi-core architectures. Proceedings of the IEEE 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, NSW, Australia."},{"key":"ref_40","doi-asserted-by":"crossref","first-page":"695","DOI":"10.1109\/TCAD.2012.2235126","article-title":"Accurate modeling of the delay and energy overhead of dynamic voltage and frequency scaling in modern microprocessors","volume":"32","author":"Park","year":"2013","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."}],"container-title":["Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-431X\/7\/1\/3\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T18:55:06Z","timestamp":1760208906000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-431X\/7\/1\/3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,12,22]]},"references-count":40,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2018,3]]}},"alternative-id":["computers7010003"],"URL":"https:\/\/doi.org\/10.3390\/computers7010003","relation":{},"ISSN":["2073-431X"],"issn-type":[{"type":"electronic","value":"2073-431X"}],"subject":[],"published":{"date-parts":[[2017,12,22]]}}}