{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,22]],"date-time":"2026-04-22T20:20:02Z","timestamp":1776889202623,"version":"3.51.2"},"reference-count":88,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2018,4,22]],"date-time":"2018-04-22T00:00:00Z","timestamp":1524355200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001858","name":"VINNOVA","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001858","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001729","name":"Stiftelsen f\u00f6r\u00a0Strategisk Forskning","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001729","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Computers"],"abstract":"<jats:p>The last ten years have seen performance and power requirements pushing computer architectures using only a single core towards so-called manycore systems with hundreds of cores on a single chip. To further increase performance and energy efficiency, we are now seeing the development of heterogeneous architectures with specialized and accelerated cores. However, designing these heterogeneous systems is a challenging task due to their inherent complexity. We proposed an approach for designing domain-specific heterogeneous architectures based on instruction augmentation through the integration of hardware accelerators into simple cores. These hardware accelerators were determined based on their common use among applications within a certain domain.The objective was to generate heterogeneous architectures by integrating many of these accelerated cores and connecting them with a network-on-chip. The proposed approach aimed to ease the design of heterogeneous manycore architectures\u2014and, consequently, exploration of the design space\u2014by automating the design steps. To evaluate our approach, we enhanced our software tool chain with a tool that can generate accelerated cores from dataflow programs. This new tool chain was evaluated with the aid of two use cases: radar signal processing and mobile baseband processing. We could achieve an approximately    4 \u00d7    improvement in performance, while executing complete applications on the augmented cores with a small impact (2.5\u201313%) on area usage. The generated accelerators are competitive, achieving more than 90% of the performance of hand-written implementations.<\/jats:p>","DOI":"10.3390\/computers7020027","type":"journal-article","created":{"date-parts":[[2018,4,24]],"date-time":"2018-04-24T04:44:48Z","timestamp":1524545088000},"page":"27","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Designing Domain-Specific Heterogeneous Architectures from Dataflow Programs"],"prefix":"10.3390","volume":"7","author":[{"given":"S\u00fcleyman","family":"Savas","sequence":"first","affiliation":[{"name":"School of Information Technology, Halmstad University, Halmstad, 301 18, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Zain","family":"Ul-Abdin","sequence":"additional","affiliation":[{"name":"School of Information Technology, Halmstad University, Halmstad, 301 18, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0562-2082","authenticated-orcid":false,"given":"Tomas","family":"Nordstr\u00f6m","sequence":"additional","affiliation":[{"name":"School of Information Technology, Halmstad University, Halmstad, 301 18, Sweden"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2018,4,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"891","DOI":"10.1109\/JSSC.2016.2638459","article-title":"KiloCore: A 32-nm 1000-processor computational array","volume":"52","author":"Bohnenstiehl","year":"2017","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_2","unstructured":"Behling, S., Bell, R., Farrell, P., Holthoff, H., O\u2019Connell, F., and Weir, W. (2001). The POWER4 Processor Introduction and Tuning Guide, IBM Redbooks."},{"key":"ref_3","unstructured":"(2017, December 20). Intel Corporation, Intel Pentium Processors. Available online: https:\/\/www.intel.com\/content\/www\/us\/en\/products\/processors\/pentium.html."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"40","DOI":"10.1109\/MSP.2011.2178495","article-title":"Scaling up MIMO: Opportunities and challenges with very large arrays","volume":"30","author":"Rusek","year":"2013","journal-title":"Signal Process. Mag. IEEE"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"186","DOI":"10.1109\/MCOM.2014.6736761","article-title":"Massive MIMO for next generation wireless systems","volume":"52","author":"Larsson","year":"2014","journal-title":"Commun. Mag. IEEE"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Barham, P., Dragovic, B., Fraser, K., Hand, S., Harris, T., Ho, A., Neugebauer, R., Pratt, I., and Warfield, A. (2003, January 19\u201322). Xen and the art of virtualization. Proceedings of the ACM SIGOPS Operating Systems Review, Bolton Landing, NY, USA.","DOI":"10.1145\/945445.945462"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Dua, R., Raja, A.R., and Kakadia, D. (2014, January 10\u201314). Virtualization vs containerization to support paas. Proceedings of the International Conference on Cloud Engineering (IC2E), Boston, MA, USA.","DOI":"10.1109\/IC2E.2014.41"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/MM.2003.1196115","article-title":"Hyperthreading technology in the netburst microarchitecture","volume":"23","author":"Koufaty","year":"2003","journal-title":"IEEE Micro"},{"key":"ref_9","unstructured":"Kumar, R., Farkas, K.I., Jouppi, N.P., Ranganathan, P., and Tullsen, D.M. (2003, January 3\u20135). Single-ISA heterogeneous multi-core architectures: The potential for processor power reduction. Proceedings of the 36th Annual IEEE\/ACM International Symposium on Microarchitecture, MICRO-36, San Diego, CA, USA."},{"key":"ref_10","first-page":"1","article-title":"State-of-the-art in heterogeneous computing","volume":"18","author":"Brodtkorb","year":"2010","journal-title":"Sci. Progr."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Liu, S., Ro, W.W., Liu, C., Salas, A.C., C\u00e9rin, C., Han, J.J., and Gaudiot, J.L. (2012, January 13\u201315). EHA: The extremely heterogeneous architecture. Proceedings of the 12th International Symposium on Pervasive Systems, Algorithms and Networks (ISPAN), San Marcos, TX, USA.","DOI":"10.1109\/I-SPAN.2012.11"},{"key":"ref_12","first-page":"45","article-title":"A survey of techniques for architecting and managing asymmetric multicore processors","volume":"48","author":"Mittal","year":"2016","journal-title":"ACM Comput. Surv. (CSUR)"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"168","DOI":"10.1016\/j.simpat.2016.12.014","article-title":"Manycore simulation for peta-scale system design: Motivation, tools, challenges and prospects","volume":"72","author":"Zarrin","year":"2017","journal-title":"Simul. Model. Pract. Theory"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"Binkert","year":"2011","journal-title":"ACM Sigarch Comput. Archit. News"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"475","DOI":"10.1145\/2508148.2485963","article-title":"ZSim: Fast and accurate microarchitectural simulation of thousand-core systems","volume":"41","author":"Sanchez","year":"2013","journal-title":"ACM Sigarch Comput. Archit. News"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Miller, J.E., Kasture, H., Kurian, G., Gruenwald, C., Beckmann, N., Celio, C., Eastep, J., and Agarwal, A. (2010, January 9\u201314). Graphite: A distributed parallel simulator for multicores. Proceedings of the 16th International Symposium on High Performance Computer Architecture (HPCA), Bangalore, India.","DOI":"10.1109\/HPCA.2010.5416635"},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Carlson, T.E., Heirmant, W., and Eeckhout, L. (2011, January 12\u201318). Sniper: Exploring the level of abstraction for scalable and accurate parallel multi-core simulation. Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis (SC), Seatle, WA, USA.","DOI":"10.1145\/2063384.2063454"},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Fu, Y., and Wentzlaff, D. (2014, January 23\u201325). PriME: A parallel and distributed simulator for thousand-core chips. Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Monterey, CA, USA.","DOI":"10.1109\/ISPASS.2014.6844467"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1145\/1054907.1054914","article-title":"Simflex: A fast, accurate, flexible full-system simulation framework for performance evaluation of server architecture","volume":"31","author":"Hardavellas","year":"2004","journal-title":"ACM Sigmetr. Perform. Eval. Rev."},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Gebrewahid, E., Yang, M., Cedersjo, G., Ul-Abdin, Z., Gaspes, V., Janneck, J.W., and Svensson, B. (2014, January 26\u201328). Realizing efficient execution of dataflow actors on manycores. Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing (EUC), Milano, Italy.","DOI":"10.1109\/EUC.2014.55"},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Bachrach, J., Vo, H., Richards, B., Lee, Y., Waterman, A., Avi\u017eienis, R., Wawrzynek, J., and Asanovi\u0107, K. (2012, January 3\u20137). Chisel: Constructing hardware in a scala embedded language. Proceedings of the 49th Annual Design Automation Conference, San Francisco, CA, USA.","DOI":"10.1145\/2228360.2228584"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Savas, S., Raase, S., Gebrewahid, E., Ul-Abdin, Z., and Nordstr\u00f6m, T. (2016, January 18\u201322). Dataflow implementation of qr decomposition on a manycore. Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, Seoul, South Korea.","DOI":"10.1145\/2934495.2934499"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"198","DOI":"10.1109\/JPROC.2003.821915","article-title":"An overview of MIMO communications-a key to gigabit wireless","volume":"92","author":"Paulraj","year":"2004","journal-title":"Proc. IEEE"},{"key":"ref_24","unstructured":"Ul-Abdin, Z., Ahlander, A., and Svensson, B. (2013, January 1\u20134). Energy-Efficient Synthetic-Aperture Radar Processing on a Manycore Architecture. Proceedings of the 2013 42nd International Conference on Parallel Processing, Lyon, France."},{"key":"ref_25","unstructured":"Neville, E.H. (1934). Iterative Interpolation, St. Joseph\u2019s IS Press."},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Eker, J., and Janneck, J.W. (2012, January 4\u20137). Dataflow programming in CAL\u2014balancing expressiveness, analyzability, and implementability. Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA, USA.","DOI":"10.1109\/ACSSC.2012.6489194"},{"key":"ref_27","unstructured":"(2018, April 04). Rocket Core Overview. Available online: http:\/\/www.lowrisc.org\/docs\/tagged-memory-v0.1\/rocket-core\/."},{"key":"ref_28","first-page":"475","article-title":"The risc-v instruction set manual, volume I: Base user-level isa","volume":"7","author":"Waterman","year":"2011","journal-title":"EECS Dep."},{"key":"ref_29","unstructured":"Asanovic, K., Avizienis, R., Bachrach, J., Beamer, S., Biancolin, D., Celio, C., Cook, H., Dabbelt, D., Hauser, J., and Izraelevitz, A. (2016). The Rocket Chip Generator, EECS Department, University of California."},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Sano, K., Hatsuda, Y., and Yamamoto, S. (2011, January 1\u20133). Scalable streaming-array of simple soft-processors for stencil computations with constant memory-bandwidth. Proceedings of the 19th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), Salt Lake City, UT, USA.","DOI":"10.1109\/FCCM.2011.12"},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1145\/2082156.2082179","article-title":"A study of an FPGA based flexible SIMD processor","volume":"39","author":"Tanabe","year":"2011","journal-title":"ACM Sigarch Comput. Archit. News"},{"key":"ref_32","unstructured":"Schurz, F., and Fey, D. (2007, January 3\u20138). A programmable parallel processor architecture in FPGAs for image processing sensors. Proceedings of the integrated design and process technology (IDPT\u201907) Conference, Antalya, Turkey."},{"key":"ref_33","unstructured":"Ajayi, T., Al-Hawaj, K., Amarnath, A., Dai, S., Davidson, S., Gao, P., Liu, G., Lotfi, A., Puscar, J., and Rao, A. (2017, January 20\u201322). Celerity: An Open-Source RISC-V Tiered Accelerator Fabric. Proceedings of the Symposium on High Performance Chips (Hot Chips), Cupertino, CA, USA."},{"key":"ref_34","unstructured":"Svensson, B. (2007, January 26\u201330). A study of design efficiency with a high-level language for FPGAs. Proceedings of the International Conference on Parallel and Distributed Processing Symposium (IPDPS), Long Beach, California, USA."},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Bjesse, P., Claessen, K., Sheeran, M., and Singh, S. (1998, January 26\u201329). Lava: Hardware design in Haskell. Proceedings of the Third ACM SIGPLAN International Conference on Functional Programming, Baltimore, MD, USA.","DOI":"10.1145\/289423.289440"},{"key":"ref_36","doi-asserted-by":"crossref","unstructured":"Baaij, C., Kooijman, M., Kuper, J., Boeijink, A., and Gerards, M. (2010, January 1\u20133). Clash: Structural descriptions of synchronous hardware using haskell. Proceedings of the 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD), Lille, France.","DOI":"10.1109\/DSD.2010.21"},{"key":"ref_37","unstructured":"(2018, April 21). CLASH, from Haskell to Hardware. Available online: http:\/\/www.clash-lang.org\/."},{"key":"ref_38","unstructured":"(2018, April 21). Vivado Design Suite, Xilinx Inc. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html\/."},{"key":"ref_39","unstructured":"(2018, April 21). Catapult C Synthesis, Calypto Design Systems. Available online: http:\/\/calypto.agranderdesign.com\/catapult_c_synthesis.php\/."},{"key":"ref_40","unstructured":"(2018, April 21). Impulse CoDeveloper, Impulse Accelerated Technologies. Available online: http:\/\/www.impulseaccelerated.com\/products.htm."},{"key":"ref_41","unstructured":"(2018, April 21). EXCite, Y Explorations Inc. Available online: http:\/\/www.yxi.com\/products.php."},{"key":"ref_42","unstructured":"(2018, April 21). Stratus High-Level Synthesis, Cadence Design Systems. Available online: https:\/\/www.cadence.com\/content\/cadence-www\/global\/en_US\/home\/tools\/digital-design-and-signoff\/synthesis\/stratus-high-level-synthesis.html\/."},{"key":"ref_43","unstructured":"(2018, April 21). Synphony C Compiler, Synopsis Inc. Available online: https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/synphony-c-compiler.html."},{"key":"ref_44","unstructured":"(2018, April 21). Catapult High-Level Synthesis Platform, Mentor Graphics. Available online: https:\/\/www.mentor.com\/hls-lp\/catapult-high-level-synthesis\/."},{"key":"ref_45","unstructured":"(2017, April 21). CyberWorkBench, NEC Corporation. Available online: http:\/\/www.nec.com\/en\/global\/prod\/cwb\/index.html?."},{"key":"ref_46","first-page":"7","article-title":"Automated generation of custom processor core from c code","volume":"2012","author":"Trajkovic","year":"2012","journal-title":"J. Elect. Comput. Eng."},{"key":"ref_47","doi-asserted-by":"crossref","unstructured":"Goodwin, D., and Petkov, D. (1, January October). Automatic generation of application specific processors. Proceedings of the 2003 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, San Jose, CA, USA.","DOI":"10.1145\/951710.951730"},{"key":"ref_48","doi-asserted-by":"crossref","first-page":"1258","DOI":"10.1109\/TC.2005.156","article-title":"Automated custom instruction generation for domain-specific processor acceleration","volume":"54","author":"Clark","year":"2005","journal-title":"IEEE Trans. Comput."},{"key":"ref_49","doi-asserted-by":"crossref","unstructured":"Koeplinger, D., Delimitrou, C., Prabhakar, R., Kozyrakis, C., Zhang, Y., and Olukotun, K. (2016, January 18\u201322). Automatic generation of efficient accelerators for reconfigurable hardware. Proceedings of the 43rd International Symposium on Computer Architecture, Seoul, South Korea.","DOI":"10.1109\/ISCA.2016.20"},{"key":"ref_50","doi-asserted-by":"crossref","unstructured":"Kathail, V., Hwang, J., Sun, W., Chobe, Y., Shui, T., and Carrillo, J. (2016, January 21\u201323). SDSoC: A Higher-level Programming Environment for Zynq SoC and Ultrascale+ MPSoC. Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, USA.","DOI":"10.1145\/2847263.2847284"},{"key":"ref_51","doi-asserted-by":"crossref","first-page":"241","DOI":"10.1007\/s11265-009-0397-5","article-title":"Synthesizing hardware from dataflow programs","volume":"63","author":"Janneck","year":"2011","journal-title":"J. Signal Process. Syst."},{"key":"ref_52","doi-asserted-by":"crossref","unstructured":"Siret, N., Wipliez, M., Nezan, J.F., and Rhatay, A. (2010, January 26\u201328). Hardware code generation from dataflow programs. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Edinburgh, UK.","DOI":"10.1109\/DASIP.2010.5706254"},{"key":"ref_53","doi-asserted-by":"crossref","unstructured":"Bezati, E., Mattavelli, M., and Janneck, J.W. (2013, January 4\u20136). High-level synthesis of dataflow programs for signal processing systems. Proceedings of the 8th International Symposium on Image and Signal Processing and Analysis (ISPA), Trieste, Italy.","DOI":"10.1109\/ISPA.2013.6703837"},{"key":"ref_54","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1016\/j.jnca.2017.04.014","article-title":"Hard: Hybrid adaptive resource discovery for jungle computing","volume":"90","author":"Zarrin","year":"2017","journal-title":"J. Netw. Comput. Appl."},{"key":"ref_55","doi-asserted-by":"crossref","first-page":"2962","DOI":"10.1016\/j.procs.2015.05.498","article-title":"A methodology for profiling and partitioning stream programs on many-core architectures","volume":"51","author":"Michalska","year":"2015","journal-title":"Procedia Comput. Sci."},{"key":"ref_56","doi-asserted-by":"crossref","first-page":"427","DOI":"10.1016\/j.jss.2016.07.025","article-title":"Hot spots profiling and dataflow analysis in custom dataflow computing SoftProcessors","volume":"125","author":"Wang","year":"2017","journal-title":"J. Syst. Softw."},{"key":"ref_57","doi-asserted-by":"crossref","unstructured":"Janneck, J.W., Miller, I.D., and Parlour, D.B. (2008, January 23\u201326). Profiling dataflow programs. Proceedings of the International Conference on Multimedia and Expo, Hannover, Germany.","DOI":"10.1109\/ICME.2008.4607622"},{"key":"ref_58","doi-asserted-by":"crossref","unstructured":"Savas, S., Gebrewahid, E., Ul-Abdin, Z., Nordstr\u00f6m, T., and Yang, M. (2014, January 20\u201322). An evaluation of code generation of dataflow languages on manycore architectures. Proceedings of the 20th International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), Chongqing, China.","DOI":"10.1109\/RTCSA.2014.6910501"},{"key":"ref_59","doi-asserted-by":"crossref","unstructured":"Olofsson, A., Nordstr\u00f6m, T., and Ul-Abdin, Z. (2014, January 2\u20135). Kickstarting high-performance energy-efficient manycore architectures with epiphany. Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, Pacific Grove, CA, USA.","DOI":"10.1109\/ACSSC.2014.7094761"},{"key":"ref_60","first-page":"13","article-title":"Survey of network-on-chip proposals","volume":"1","author":"Salminen","year":"2008","journal-title":"White Pap. OCP-IP"},{"key":"ref_61","first-page":"22","article-title":"Survey of NoC and programming models proposals for MPSoC","volume":"9","author":"Joven","year":"2012","journal-title":"Int. J. Comput. Sci. Issues"},{"key":"ref_62","first-page":"21","article-title":"Survey of network on chip (noc) architectures & contributions","volume":"3","author":"Agarwal","year":"2009","journal-title":"J. Eng. Comput. Archit."},{"key":"ref_63","doi-asserted-by":"crossref","first-page":"1907","DOI":"10.1016\/S0167-8191(99)00070-8","article-title":"Advances in the dataflow computational model","volume":"25","author":"Najjar","year":"1999","journal-title":"Parallel Comput."},{"key":"ref_64","doi-asserted-by":"crossref","unstructured":"Horowitz, E. (1984). Data Flow Programming Languages. Fundamentals of Programming Languages, Springer.","DOI":"10.1007\/978-3-642-69406-6"},{"key":"ref_65","doi-asserted-by":"crossref","first-page":"251","DOI":"10.1007\/s11265-009-0399-3","article-title":"Overview of the MPEG Reconfigurable Video Coding Framework","volume":"63","author":"Bhattacharyya","year":"2011","journal-title":"J. Signal Process. Syst."},{"key":"ref_66","unstructured":"Savas, S. (2011). Implementation and Evaluation of Mpeg-4 Simple Profile Decoder on a Massively Parallel Processor Array. [Master\u2019s Thesis, Halmstad University]."},{"key":"ref_67","doi-asserted-by":"crossref","unstructured":"Nethercote, N., and Seward, J. (2007, January 11\u201313). Valgrind: A framework for heavyweight dynamic binary instrumentation. Proceedings of the 28th ACM SIGPLAN Conference on Programming Language Design and Implementation, San Diego, CA, USA.","DOI":"10.1145\/1250734.1250746"},{"key":"ref_68","unstructured":"Fenlason, J., and Stallman, R. (2018, April 21). GNU Gprof. GNU Binutils. Available online: http:\/\/www.gnu.org\/software\/binutils."},{"key":"ref_69","unstructured":"Casale-Brunet, S., Alberti, C., Mattavelli, M., and Janneck, J.W. (2013, January 8\u201310). Turnus: A unified dataflow design space exploration framework for heterogeneous parallel systems. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Cagliari, Italy."},{"key":"ref_70","unstructured":"Yviquel, H., Lorence, A., Jerbi, K., Cocherel, G., Sanchez, A., and Raulet, M. (2013, January 21\u201325). Orcc: Multimedia Development Made Easy. Proceedings of the 21st ACM International Conference on Multimedia, Barcelona, Spain."},{"key":"ref_71","doi-asserted-by":"crossref","unstructured":"Pelcat, M., Nezan, J.F., Piat, J., Croizer, J., and Aridhi, S. (2009, January 22\u201324). A system-level architecture model for rapid prototyping of heterogeneous multicore embedded systems. Proceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), Sophia Antipolis, France.","DOI":"10.1155\/2009\/598529"},{"key":"ref_72","doi-asserted-by":"crossref","unstructured":"Atasu, K., Dimond, R.G., Mencer, O., Luk, W., \u00d6zturan, C., and D\u00fcndar, G. (2007, January 16\u201320). Optimizing instruction-set extensible processors under data bandwidth constraints. Proceedings of the Conference on Design, Automation and Test in Europe, EDA Consortium, Nice, France.","DOI":"10.1109\/DATE.2007.364657"},{"key":"ref_73","doi-asserted-by":"crossref","unstructured":"Haa\u00df, M., Bauer, L., and Henkel, J. (2014, January 12\u201317). Automatic custom instruction identification in memory streaming algorithms. Proceedings of the 2014 International Conference on Compilers, Architecture and Synthesis for Embedded Systems, New Delhi, India.","DOI":"10.1145\/2656106.2656114"},{"key":"ref_74","doi-asserted-by":"crossref","unstructured":"Janneck, J. (2011, January 6\u20139). A machine model for dataflow actors and its applications. Proceedings of the Conference Record of the 45th Asilomar Conference on Signals, Systems and Computers (ASILOMAR), Pacific Grove, CA, USA.","DOI":"10.1109\/ACSSC.2011.6190107"},{"key":"ref_75","doi-asserted-by":"crossref","unstructured":"Karlsson, A., Sohl, J., and Liu, D. (2015, January 21\u201324). Epuma: A processor architecture for future dsp. Proceedings of the International Conference on Digital Signal Processing (DSP), Singapore.","DOI":"10.1109\/ICDSP.2015.7251870"},{"key":"ref_76","unstructured":"Zhang, C. (2014). Dynamically Reconfigurable Architectures for Real-Time Baseband Processing. [Ph.D. Dissertation, Lund University]."},{"key":"ref_77","doi-asserted-by":"crossref","unstructured":"Savas, S., Hertz, E., Nordstr\u00f6m, T., and Ul-Abdin, Z. (2017, January 3\u20135). Efficient Single-Precision Floating-Point Division Using Harmonized Parabolic Synthesis. Proceedings of the Annual Symposium on VLSI (ISVLSI), Bochum, Germany.","DOI":"10.1109\/ISVLSI.2017.28"},{"key":"ref_78","unstructured":"Odersky, M. (2014). The Scala Language Specification, Programming Methods Laboratory, EPFL. Version 2.9."},{"key":"ref_79","unstructured":"Asanovic, K., Patterson, D.A., and Celio, C. (2015). The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor, University of California at Berkeley. Technical Report."},{"key":"ref_80","unstructured":"Celio, C. (2017, November 03). RISC-V Sodor CPU. Available online: https:\/\/github.com\/ucb-bar\/riscv-sodor."},{"key":"ref_81","unstructured":"Clifford, W. (2017, November 03). PicoRV32\u2014A Size-Optimized RISC-V CPU. Available online: https:\/\/github.com\/cliffordwolf\/picorv32."},{"key":"ref_82","unstructured":"Syntacore (2017, November 03). SCR1\u2014An Open-Source RISC-V Compatible MCU Core. Available online: https:\/\/github.com\/syntacore\/scr1."},{"key":"ref_83","unstructured":"Yarp, C. (2017, November 10). An Introduction to the Rocket Custom Coprocessor Interface. Available online: http:\/\/c199.eecs.berkeley.edu\/~cs250\/sp16\/disc\/Disc02.pdf."},{"key":"ref_84","unstructured":"Snyder, W., Galbi, D., and Wasson, P. (2017, November 10). Verilator, Verilog HDL Simulator. Available online: https:\/\/www.veripool.org\/wiki\/verilator."},{"key":"ref_85","doi-asserted-by":"crossref","first-page":"467","DOI":"10.1016\/S0169-7161(05)80137-3","article-title":"13 Computation using the QR decomposition","volume":"9","author":"Goodall","year":"1993","journal-title":"Handb. Stat."},{"key":"ref_86","unstructured":"Savas, S. (2009). Linear Algebra for Array Signal Processing on a Massively Parallel Dataflow Architecture. [Bachelor\u2019s Thesis, School of Information Technology]."},{"key":"ref_87","unstructured":"Gebrewahid, E. (2017). Tools to Compile Dataflow Programs for Manycores. [Ph.D. Thesis, Halmstad University Press]."},{"key":"ref_88","unstructured":"IEEE Task P754 (2008). IEEE 754-2008, Standard for Floating-Point Arithmetic, IEEE Press."}],"container-title":["Computers"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2073-431X\/7\/2\/27\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T15:01:41Z","timestamp":1760194901000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2073-431X\/7\/2\/27"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,22]]},"references-count":88,"journal-issue":{"issue":"2","published-online":{"date-parts":[[2018,6]]}},"alternative-id":["computers7020027"],"URL":"https:\/\/doi.org\/10.3390\/computers7020027","relation":{},"ISSN":["2073-431X"],"issn-type":[{"value":"2073-431X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4,22]]}}}