{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,13]],"date-time":"2026-06-13T01:56:30Z","timestamp":1781315790807,"version":"3.54.1"},"reference-count":31,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T00:00:00Z","timestamp":1624838400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>With the continuous scaling of CMOS technology, which has now reached the 3 nm node at production level, static power begins to dominate the power consumption of nanometer CMOS integrated circuits. A novel class of security attacks to cryptographic circuits which exploit the correlation between the static power and the secret keys was introduced more than ten years ago, and, since then, several successful key recovery experiments have been reported. These results clearly demonstrate that attacks exploiting static power (AESP) represent a serious threat for cryptographic systems implemented in nanometer CMOS technologies. In this work, we analyze the effectiveness of the Standard Cell Delay-based Precharge Logic (SC-DDPL) style in counteracting static power side-channel attacks. Experimental results on an FPGA implementation of a compact PRESENT crypto-core show that the SC-DDPL implementation allows a great improvement of all the security metrics with respect to the standard CMOS implementation and other state-of-the-art countermeasures such as WDDL and MDPL.<\/jats:p>","DOI":"10.3390\/cryptography5030016","type":"journal-article","created":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T13:39:22Z","timestamp":1624887562000},"page":"16","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["SC-DDPL as a Countermeasure against Static Power Side-Channel Attacks"],"prefix":"10.3390","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6947-4410","authenticated-orcid":false,"given":"Davide","family":"Bellizia","sequence":"first","affiliation":[{"name":"ICTEAM\/ELEN Crypto Group, Universit\u00e9 Catholique de Louvain, 1348 Louvain-la-Neuve, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9990-4875","authenticated-orcid":false,"given":"Riccardo","family":"Della Sala","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria Elettronica e Telecomunicazioni (DIET), Sapienza Universit\u00e0 di Roma, 00185 Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5650-8212","authenticated-orcid":false,"given":"Giuseppe","family":"Scotti","sequence":"additional","affiliation":[{"name":"Dipartimento di Ingegneria Elettronica e Telecomunicazioni (DIET), Sapienza Universit\u00e0 di Roma, 00185 Rome, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2021,6,28]]},"reference":[{"key":"ref_1","first-page":"104","article-title":"Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems","volume":"Volume 1109","author":"Koblitz","year":"1996","journal-title":"Advances in Cryptology\u2014CRYPTO \u201996, Proceedings of the 16th Annual International Cryptology Conference, Santa Barbara, CA, USA, 18\u201322 August 1996"},{"key":"ref_2","first-page":"388","article-title":"Differential Power Analysis","volume":"Volume 1666","author":"Wiener","year":"1999","journal-title":"Advances in Cryptology\u2014CRYPTO \u201999, Proceedings of the 19th Annual International Cryptology Conference, Santa Barbara, CA, USA, 15\u201319 August 1999"},{"key":"ref_3","first-page":"200","article-title":"ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smart Cards","volume":"Volume 2140","author":"Attali","year":"2001","journal-title":"Proceedings of the Smart Card Programming and Security, International Conference on Research in Smart Cards, E-smart 2001"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"355","DOI":"10.1109\/TCSI.2009.2019411","article-title":"Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits","volume":"57-I","author":"Alioto","year":"2010","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_5","unstructured":"Tiri, K., and Verbauwhede, I. (2004, January 16\u201320). A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation. Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), Paris, France."},{"key":"ref_6","first-page":"172","article-title":"Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints","volume":"Volume 3659","author":"Rao","year":"2005","journal-title":"Cryptographic Hardware and Embedded Systems\u2014CHES 2005, Proceedings of the 7th International Workshop, Edinburgh, UK, 29 August\u20131 September 2005"},{"key":"ref_7","first-page":"19","article-title":"Scaling Trends for Dual-Rail Logic Styles Against Side-Channel Attacks: A Case-Study","volume":"Volume 10348","author":"Guilley","year":"2017","journal-title":"Proceedings of the Constructive Side-Channel Analysis and Secure Design\u20148th International Workshop, COSADE 2017"},{"key":"ref_8","unstructured":"Tiri, K., Akmal, M., and Verbauwhede, I. (2002, January 24\u201326). A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards. Proceedings of the 28th European Solid-State Circuits Conference, Florence, Italy."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"He, W., Otero, A., de la Torre, E., and Riesgo, T. (2012, January 5\u20137). Automatic generation of identical routing pairs for FPGA implemented DPL logic. Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2012, Cancun, Mexico.","DOI":"10.1109\/ReConFig.2012.6416733"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"1147","DOI":"10.1109\/TVLSI.2010.2046505","article-title":"Delay-Based Dual-Rail Precharge Logic","volume":"19","author":"Bucci","year":"2011","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1007\/s13389-015-0096-z","article-title":"Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks","volume":"5","author":"Bongiovanni","year":"2015","journal-title":"J. Cryptogr. Eng."},{"key":"ref_12","first-page":"3874","article-title":"TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65 nm CMOS and Experimental Results","volume":"65-I","author":"Bellizia","year":"2018","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"2317","DOI":"10.1109\/TCSI.2020.2979831","article-title":"SC-DDPL: A Novel Standard-Cell Based Approach for Counteracting Power Analysis Attacks in the Presence of Unbalanced Routing","volume":"67-I","author":"Bellizia","year":"2020","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"329","DOI":"10.1109\/TETC.2016.2563322","article-title":"Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications","volume":"5","author":"Bellizia","year":"2017","journal-title":"IEEE Trans. Emerg. Top. Comput."},{"key":"ref_15","unstructured":"Bellizia, D. (2018). Design Methodologies for Cryptographic Hardware with Countermeasures against Side Channel Attacks. [Ph.D. Thesis, Sapienza Universit\u00e0 di Roma, DIET]. Available online: http:\/\/hdl.handle.net\/11573\/1094643."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Chandrakasan, A.P., Bowhill, W.J., and Fox, F. (2000). Design of High-Performance Microprocessor Circuits, Wiley-IEEE Press. [1st ed.].","DOI":"10.1109\/9780470544365"},{"key":"ref_17","unstructured":"Narendra, S.G., and Chandrakasan, A. (2005). Leakage in Nanometer CMOS Technologies, Springer."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"376","DOI":"10.1109\/TVLSI.2019.2948141","article-title":"Static Power Side-Channel Analysis\u2014An Investigation of Measurement Factors","volume":"28","author":"Moos","year":"2020","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"233","DOI":"10.46586\/tches.v2019.i3.233-256","article-title":"Exploring the Effect of Device Aging on Static Power Analysis Attacks","volume":"2019","author":"Karimi","year":"2019","journal-title":"IACR Trans. Cryptogr. Hardw. Embed. Syst."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"202","DOI":"10.46586\/tches.v2019.i3.202-232","article-title":"Static Power SCA of Sub-100 nm CMOS ASICs and the Insecurity of Masking Schemes in Low-Noise Environments","volume":"2019","author":"Moos","year":"2019","journal-title":"IACR Trans. Cryptogr. Hardw. Embed. Syst."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"79","DOI":"10.1007\/978-3-319-57339-7_5","article-title":"Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications","volume":"Volume 10239","author":"Joye","year":"2017","journal-title":"Proceedings of the Progress in Cryptology\u2014AFRICACRYPT 2017\u20149th International Conference on Cryptology in Africa"},{"key":"ref_22","first-page":"562","article-title":"Side-Channel Leakage through Static Power\u2014Should We Care about in Practice?","volume":"Volume 8731","author":"Batina","year":"2014","journal-title":"Proceedings of the Cryptographic Hardware and Embedded Systems\u2014CHES 2014\u201416th International Workshop"},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"Bellizia, D., Scotti, G., and Trifiletti, A. (2016, January 23\u201325). Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power. Proceedings of the 2016 MIXDES\u201423rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland.","DOI":"10.1109\/MIXDES.2016.7529734"},{"key":"ref_24","unstructured":"Nebel, W., and Atienza, D. (2015, January 9\u201313). Side-channel attacks from static power: When should we care?. Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, DATE 2015, Grenoble, France."},{"key":"ref_25","first-page":"222","article-title":"Hardware Countermeasures against DPA? A Statistical Analysis of Their Effectiveness","volume":"Volume 2964","author":"Okamoto","year":"2004","journal-title":"Proceedings of the Topics in Cryptology\u2014CT-RSA 2004, The Cryptographers\u2019 Track at the RSA Conference 2004"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"427","DOI":"10.1007\/978-3-540-74735-2_29","article-title":"Information Theoretic Evaluation of Side-Channel Resistant Logic Styles","volume":"Volume 4727","author":"Paillier","year":"2007","journal-title":"Proceedings of the Cryptographic Hardware and Embedded Systems\u2014CHES 2007, 9th International Workshop"},{"key":"ref_27","unstructured":"Becker, G., Cooper, J., DeMulder, E., Goodwill, G., Jaffe, J., Kenworthy, G., Kouzminov, T., Leiserson, A., Marson, M., and Rohatgi, P. (2013, January 24\u201326). Test Vector Leakage Assessment (TVLA) Methodology in Practice. Proceedings of the International Cryptographic Module Conference 2013, Gaithersburg, MD, USA."},{"key":"ref_28","first-page":"240","article-title":"From Improved Leakage Detection to the Detection of Points of Interests in Leakage Traces","volume":"Volume 9665","author":"Fischlin","year":"2016","journal-title":"Proceedings of the Advances in Cryptology\u2014EUROCRYPT 2016\u201435th Annual International Conference on the Theory and Applications of Cryptographic Techniques"},{"key":"ref_29","unstructured":"Fant, K.M., and Brandt, S.A. (1996, January 19\u201323). NULL Convention Logic\/sup TM\/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis. Proceedings of the 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP \u201996), Chicago, IL, USA."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"450","DOI":"10.1007\/978-3-540-74735-2_31","article-title":"PRESENT: An Ultra-Lightweight Block Cipher","volume":"Volume 4727","author":"Paillier","year":"2007","journal-title":"Proceedings of the Cryptographic Hardware and Embedded Systems\u2014CHES 2007, 9th International Workshop"},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Bellizia, D., Cellucci, D., Stefano, V.D., Scotti, G., and Trifiletti, A. (2017, January 4\u20136). Novel measurements setup for attacks exploiting static power using DC pico-ammeter. Proceedings of the 2017 European Conference on Circuit Theory and Design, ECCTD 2017, Catania, Italy.","DOI":"10.1109\/ECCTD.2017.8093333"}],"container-title":["Cryptography"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2410-387X\/5\/3\/16\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T06:25:32Z","timestamp":1760163932000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2410-387X\/5\/3\/16"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,6,28]]},"references-count":31,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2021,9]]}},"alternative-id":["cryptography5030016"],"URL":"https:\/\/doi.org\/10.3390\/cryptography5030016","relation":{},"ISSN":["2410-387X"],"issn-type":[{"value":"2410-387X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,6,28]]}}}