{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,2]],"date-time":"2025-11-02T05:29:41Z","timestamp":1762061381193,"version":"build-2065373602"},"reference-count":24,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T00:00:00Z","timestamp":1659484800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"U.S. Department of Energy\u2019s National Nuclear Security Administration","award":["SAND2022-10390 J"],"award-info":[{"award-number":["SAND2022-10390 J"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>Advanced, superscalar microprocessors (\u03bcP) are highly susceptible to wear-out failures because of their highly complex, densely packed circuit structure and extreme operational frequencies. Although many types of fault detection and mitigation strategies have been proposed, none have addressed the specific problem of detecting faults that lead to information leakage events on I\/O channels of the \u03bcP. Information leakage can be defined very generally as any type of output that the executing program did not intend to produce. In this work, we restrict this definition to output that represents a security concern, and in particular, to the leakage of plaintext or encryption keys, and propose a counter-based countermeasure to detect faults that cause this type of leakage event. Fault injection (FI) experiments are carried out on two RISC-V microprocessors emulated as soft cores on a Xilinx multi-processor System-on-chip (MPSoC) FPGA. The \u03bcP designs are instrumented with a set of counters that records the number of transitions that occur on internal nodes. The transition counts are collected from all internal nodes under both fault-free and faulty conditions, and are analyzed to determine which counters provide the highest fault coverage and lowest latency for detecting leakage faults. We show that complete coverage of all leakage faults is possible using only a single counter strategically placed within the branch compare logic of the \u03bcPs.<\/jats:p>","DOI":"10.3390\/cryptography6030038","type":"journal-article","created":{"date-parts":[[2022,8,3]],"date-time":"2022-08-03T20:52:01Z","timestamp":1659559921000},"page":"38","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor"],"prefix":"10.3390","volume":"6","author":[{"suffix":"Jr.","given":"Donald E.","family":"Owen","sequence":"first","affiliation":[{"name":"Advanced CMOS Products\/Design, Sandia National Laboratories, Albuquerque, NM 87131, USA"}]},{"given":"Jithin","family":"Joseph","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1876-117X","authenticated-orcid":false,"given":"Jim","family":"Plusquellic","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"given":"Tom J.","family":"Mannos","sequence":"additional","affiliation":[{"name":"Advanced CMOS Products\/Design, Sandia National Laboratories, Albuquerque, NM 87131, USA"}]},{"given":"Brian","family":"Dziki","sequence":"additional","affiliation":[{"name":"Information Assurance Research, Department of Defense, Fort G. G. Meade, Anne Arundel County, MD 24003, USA"}]}],"member":"1968","published-online":{"date-parts":[[2022,8,3]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1109\/2.386985","article-title":"Fault injection: A method for validating computer-system dependability","volume":"28","author":"Clark","year":"1995","journal-title":"Computer"},{"key":"ref_2","unstructured":"Siewiorek, D., and Swarz, R. (1982). The Theory and Practice of Reliable System Design, Digital Press."},{"key":"ref_3","unstructured":"Wakerly, J.F. (1978). Error Detecting Codes, Self-Checking Circuits and Applications, North\u2013Holland."},{"key":"ref_4","unstructured":"Rotenberg, E. (1999, January 15\u201318). AR-SMT: A microarchitectural approach to fault tolerance in microprocessors. Proceedings of the Twenty-Ninth Annual International Symposium on Fault-Tolerant Computing (Cat. No.99CB36352), Madison, WI, USA."},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Pellegrini, A., Smolinski, R., Chen, L., Fu, X., Hari, S.K.S., Jiang, J., Adve, S.V., Austin, T., and Bertacco, V. (2012, January 12\u201316). CrashTest\u2019ing SWAT: Accurate, gate-level evaluation of symptom-based resiliency solutions. Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany.","DOI":"10.1109\/DATE.2012.6176660"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"265","DOI":"10.1145\/1353536.1346315","article-title":"Understanding the propagation of hard errors to software and implications for resilient system design","volume":"43","author":"Li","year":"2008","journal-title":"ACM Sigplan Not."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Constantinides, K., Mutlu, O., Austin, T., and Bertacco, V. (2007, January 1\u20135). Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. Proceedings of the 40th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO 2007), Chicago, IL, USA.","DOI":"10.1109\/MICRO.2007.34"},{"key":"ref_8","unstructured":"(2022, March 10). Rocket Chip Generator. Available online: https:\/\/github.com\/chipsalliance\/rocket-chip."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"438","DOI":"10.1109\/TCAD.2021.3065915","article-title":"Information Leakage Analysis using a Co-design-Based Fault Injection Technique on a RISC-V Microprocessor","volume":"41","author":"Plusquellic","year":"2021","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_10","unstructured":"Skordal, K.K. (2022, July 28). A Simple RISC-V Processor for Use in FPGA Designs. Available online: https:\/\/github.com\/skordal\/potato."},{"key":"ref_11","unstructured":"Asanovic, K., Avizienis, R., Bachrach, J., Beamer, S., Biancolin, D., Celio, C., Cook, H., Dabbelt, D., Hauser, J., and Izraelevitz, A. (2022, March 03). The Rocket Chip Generator. EECS Dep. Univ. Calif. Berkeley Tech. Rep. UCB\/EECS-2016-17., Available online: https:\/\/www2.eecs.berkeley.edu\/Pubs\/TechRpts\/2016\/EECS-2016-17.pdf."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Mannos, T.J., Dziki, B., and Sharif, M. (2019, January 24\u201326). Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation. Proceedings of the 2019 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays, Seaside, CA, USA.","DOI":"10.1145\/3289602.3293931"},{"key":"ref_13","unstructured":"(2022, March 10). Advanced Encryption Standard. Available online: https:\/\/en.wikipedia.org\/wiki\/Advanced_Encryption_Standard."},{"key":"ref_14","unstructured":"Austin, T. (1999, January 16\u201318). DIVA: A reliable substrate for deep submicron microarchitecture design. Proceedings of the MICRO-32, 32nd Annual ACM\/IEEE International Symposium on Microarchitecture, Haifa, Israel."},{"key":"ref_15","unstructured":"Weaver, C., and Austin, T. (2001, January 1\u20134). A fault tolerant approach to microprocessor design. Proceedings of the 2001 International Conference on Dependable Systems and Networks, Gothenburg, Sweden."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Pellegrini, A., Constantinides, K., Zhang, D., Sudhakar, S., Bertacco, V., and Austin, T. (2008, January 12\u201315). CrashTest: A fast high-fidelity FPGA-based resiliency analysis framework. Proceedings of the 2008 IEEE International Conference on Computer Design, Lake Tahoe, CA, USA.","DOI":"10.1109\/ICCD.2008.4751886"},{"key":"ref_17","unstructured":"Sergeykhbr (2022, March 10). System-On-Chip Template Based on Synthesizable Processor Compliant with the RISC-v Architecture. Available online: https:\/\/github.com\/sergeykhbr\/riscv_vhdl."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"41302","DOI":"10.1109\/ACCESS.2018.2858773","article-title":"Impact of microarchitectural differences of RISC-V processor cores on soft error effects","volume":"6","author":"Cho","year":"2018","journal-title":"IEEE Access"},{"key":"ref_19","unstructured":"(2022, March 10). PetaLinux Tools. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/embedded-software\/petalinux-sdk.htm."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"105","DOI":"10.1016\/j.mejo.2016.04.006","article-title":"ASAP7: A 7-nm finFET predictive process design kit","volume":"53","author":"Clark","year":"2016","journal-title":"Microelectron. J."},{"key":"ref_21","unstructured":"(2022, March 10). Synopsys Design Compiler. Available online: https:\/\/www.synopsys.com\/implementation-and-signoff\/rtl-synthesis-test\/design-compiler-graphical.html."},{"key":"ref_22","unstructured":"(2022, March 10). Cadence Innovus Implementation System. Available online: https:\/\/www.cadence.com\/en_US\/home\/tools\/digital-design-and-signoff\/soc-implementation-and-floorplanning\/innovus-implementation-system.html."},{"key":"ref_23","unstructured":"(2022, March 10). Vivado Design Suite. Available online: https:\/\/www.xilinx.com\/products\/design-tools\/vivado.html."},{"key":"ref_24","unstructured":"(2022, March 10). High Level View of Rocket Pipeline. Available online: https:\/\/www-inst.eecs.berkeley.edu\/~cs250\/fa13\/handouts\/lab2-riscv.pdf#13."}],"container-title":["Cryptography"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2410-387X\/6\/3\/38\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T00:01:38Z","timestamp":1760140898000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2410-387X\/6\/3\/38"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,8,3]]},"references-count":24,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2022,9]]}},"alternative-id":["cryptography6030038"],"URL":"https:\/\/doi.org\/10.3390\/cryptography6030038","relation":{},"ISSN":["2410-387X"],"issn-type":[{"type":"electronic","value":"2410-387X"}],"subject":[],"published":{"date-parts":[[2022,8,3]]}}}