{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T00:29:52Z","timestamp":1775521792759,"version":"3.50.1"},"reference-count":28,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2022,11,11]],"date-time":"2022-11-11T00:00:00Z","timestamp":1668124800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>Physical unclonable functions (PUFs) are gaining traction as an attractive alternative to generating and storing device keying material over traditional secure non-volatile memory (NVM) technologies. In this paper, we propose an engineered delay-based PUF called the shift-register, reconvergent-fanout (SiRF) PUF, and present an analysis of the statistical quality of its bitstrings using data collected from a set of FPGAs subjected to extended industrial temperature-voltage environmental conditions. The SiRF PUF utilizes the Xilinx shift register primitive and an engineered network of logic gates that are designed to distribute signal paths over a wide region of the FPGA fabric using a MUXing scheme similar in principle to the shift-rows permutation function within the Advanced Encryption Standard algorithm. The shift register is utilized in a unique fashion to enable individual paths through a Xilinx 5-input LUT to be selected as a source of entropy by the challenge. The engineered logic gate network utilizes reconvergent-fanout as a means of adding entropy, eliminating bias and increasing uncertainty with respect to which paths are actually being timed and used in post-processing to produce the secret key or authentication bitstring. The SiRF PUF is a strong PUF build on top of a network with 10\u2019s of millions of possible paths.<\/jats:p>","DOI":"10.3390\/cryptography6040059","type":"journal-article","created":{"date-parts":[[2022,11,14]],"date-time":"2022-11-14T04:24:10Z","timestamp":1668399850000},"page":"59","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA"],"prefix":"10.3390","volume":"6","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1876-117X","authenticated-orcid":false,"given":"Jim","family":"Plusquellic","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]}],"member":"1968","published-online":{"date-parts":[[2022,11,11]]},"reference":[{"key":"ref_1","unstructured":"Lofstrom, K., Daasch, W., and Taylor, D. (2000, January 9). IC identification circuit using device mismatch. Proceedings of the 2000 IEEE International Solid-State Circuits Conference, Digest of Technical Papers (Cat. No.00CH37056), San Francisco, CA, USA."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Gassend, B., Clarke, D., van Dijk, M., and Devadas, S. (2002). Silicon Physical Random Functions, Association for Computing Machinery.","DOI":"10.1145\/586110.586132"},{"key":"ref_3","unstructured":"Lee, J., Lim, D., Gassend, B., Suh, G., van Dijk, M., and Devadas, S. (2004, January 17\u201319). A technique to build a secret key in integrated circuits for identification and authentication applications. Proceedings of the 2004 Symposium on VLSI Circuits, Digest of Technical Papers (IEEE Cat. No. 04CH37525), Honolulu, HI, USA."},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Suh, G.E., and Devadas, S. (2007, January 4\u20138). Physical unclonable functions for device authentication and secret key generation. Proceedings of the 2007 44th ACM\/IEEE Design Automation Conference, San Diego, CA, USA.","DOI":"10.1109\/DAC.2007.375043"},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Su, Y., Holleman, J., and Otis, B. (2007, January 11\u201315). A 1.6 pJ\/bit 96% Stable Chip-ID Generating Circuit using Process Variations. In Proceedings of the 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2007.373466"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Paillier, P., and Verbauwhede, I. (2007, January 10\u201313). FPGA Intrinsic PUFs and Their Use for IP Protection. Proceedings of the Cryptographic Hardware and Embedded Systems\u2014CHES 2007, Vienna, Austria.","DOI":"10.1007\/978-3-540-74735-2"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Helinski, R., Acharyya, D., and Plusquellic, J. (2009, January 26\u201331). A physical unclonable function defined using power distribution system equivalent resistance variations. Proceedings of the 2009 46th ACM\/IEEE Design Automation Conference, San Francisco, CA, USA.","DOI":"10.1145\/1629911.1630089"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Kamal, K., and Muresan, R. (May, January 30). Capacitive physically unclonable function. Proceedings of the 2017 IEEE 30th Canadian Conference on Electrical and Computer Engineering (CCECE), Windsor, ON, Canada.","DOI":"10.1109\/CCECE.2017.7946730"},{"key":"ref_9","unstructured":"Maes, R., and Tuyls, P.V.I. (2008, January 13\u201314). Intrinsic PUFs from flip-flops on reconfigurable devices. Proceedings of the 3rd Benelux Workshop on Information and System Security (WISSec 2008), Eindhoven, The Netherlands."},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Kumar, S.S., Guajardo, J., Maes, R., Schrijen, G.J., and Tuyls, P. (2008, January 9). Extended Abstract: The Butterfly PUF Protecting IP on every FPGA. Proceedings of the Hardware-Oriented Security and Trust Workshop (HOST2008), Anaheim, CA, USA.","DOI":"10.1109\/HST.2008.4559053"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1109\/TCAD.2017.2702607","article-title":"Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF","volume":"37","author":"Marchand","year":"2018","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Della Sala, R., Bellizia, D., and Scotti, G. (2021). A Novel Ultra-Compact FPGA PUF: The DD-PUF. Cryptography, 5.","DOI":"10.3390\/cryptography5030023"},{"key":"ref_13","first-page":"2972","article-title":"A Lightweight FPGA Compatible Weak-PUF Primitive Based on XOR Gates","volume":"69","author":"Bellizia","year":"2022","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Gu, C., Murphy, J., and O\u2019Neill, M. (2014, January 1\u20135). A unique and robust single slice FPGA identification generator. Proceedings of the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, VIC, Australia.","DOI":"10.1109\/ISCAS.2014.6865362"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"227","DOI":"10.1007\/s13389-020-00244-5","article-title":"A large-scale comprehensive evaluation of single-slice ring oscillator and PicoPUF bit cells on 28-nm Xilinx FPGAs","volume":"11","author":"Gu","year":"2021","journal-title":"J. Cryptogr. Eng."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Huang, Z., Li, L., Chen, Y., Li, Z., Wang, Q., and Jiang, X. (2021). RPPUF: An Ultra-Lightweight Reconfigurable Pico-Physically Unclonable Function for Resource-Constrained IoT Devices. Electronics, 10.","DOI":"10.3390\/electronics10233039"},{"key":"ref_17","unstructured":"Huang, J., and Lach, J. (2008, January 9). IC Activation and User Authentication for Security-Sensitive Systems. Proceedings of the Workshop on Hardware-Oriented Security and Trust, Anaheim, CA, USA."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1109\/MDT.2013.2247459","article-title":"HELP: A hardware-embedded delay PUF","volume":"30","author":"Aarestad","year":"2013","journal-title":"IEEE Des. Test"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Che, W., Martin, M., Pocklassery, G., Kajuluri, V.K., Saqib, F., and Plusquellic, J. (2017). A Privacy-Preserving, Mutual PUF-Based Authentication Protocol. Cryptography, 1.","DOI":"10.3390\/cryptography1010003"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Che, W., Kajuluri, V.K., Martin, M., Saqib, F., and Plusquellic, J. (2017). Analysis of Entropy in a Hardware-Embedded Delay PUF. Cryptography, 1.","DOI":"10.3390\/cryptography1010008"},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Che, W., Kajuluri, V.K., Saqib, F., and Plusquellic, J. (2017). Leveraging Distributions in Physical Unclonable Functions. Cryptography, 1.","DOI":"10.3390\/cryptography1030017"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Sauer, M., Raiola, P., Feiten, L., Becker, B., R\u00fchrmair, U., and Polian, I. (2017, January 27\u201331). Sensitized path PUF: A lightweight embedded physical unclonable function. Proceedings of the 2017 Design, Automation Test in Europe Conference Exhibition (DATE), Lausanne, Switzerland.","DOI":"10.23919\/DATE.2017.7927076"},{"key":"ref_23","unstructured":"Tiri, K., and Verbauwhede, I. (2004, January 16\u201320). A logic level design methodology for a secure DPA resistant ASIC or FPGA implementation. Proceedings of the 2004 Design, Automation and Test in Europe Conference and Exhibition, Paris, France."},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Owen, D., Heeger, D., Chan, C., Che, W., Saqib, F., Areno, M., and Plusquellic, J. (2018). An autonomous, self-authenticating, and self-contained secure boot process for field-programmable gate arrays. Cryptography, 2.","DOI":"10.3390\/cryptography2030015"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Ju, J., Chakraborty, R., Lamech, C., and Plusquellic, J. (, January 2\u20133). Stability analysis of a physical unclonable function based on metal resistance variations. Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), Austin, TX, USA.","DOI":"10.1109\/HST.2013.6581580"},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Heeger, D., and Plusquellic, J. (2020, January 25\u201327). Analysis of IoT Authentication Over LoRa. Proceedings of the 2020 16th International Conference on Distributed Computing in Sensor Systems (DCOSS), Marina del Rey, CA, USA.","DOI":"10.1109\/DCOSS49796.2020.00078"},{"key":"ref_27","unstructured":"(2022, September 10). A Statistical Test Suite for Random and Pseudorandom Number Generators for Cryptographic Applications, Available online: https:\/\/nvlpubs.nist.gov\/nistpubs\/legacy\/sp\/nistspecialpublication800-22r1a.pdf."},{"key":"ref_28","unstructured":"(2022, September 10). ZedBoard. Available online: https:\/\/www.xilinx.com\/products\/boards-and-kits\/1-8dyf-11.html."}],"container-title":["Cryptography"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2410-387X\/6\/4\/59\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T01:14:38Z","timestamp":1760145278000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2410-387X\/6\/4\/59"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,11,11]]},"references-count":28,"journal-issue":{"issue":"4","published-online":{"date-parts":[[2022,12]]}},"alternative-id":["cryptography6040059"],"URL":"https:\/\/doi.org\/10.3390\/cryptography6040059","relation":{},"ISSN":["2410-387X"],"issn-type":[{"value":"2410-387X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,11,11]]}}}