{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,28]],"date-time":"2026-02-28T07:17:00Z","timestamp":1772263020167,"version":"3.50.1"},"reference-count":33,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2023,2,6]],"date-time":"2023-02-06T00:00:00Z","timestamp":1675641600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>The Internet of Things (IoT) is an intelligent technology applied to various fields like agriculture, healthcare, automation, and defence. Modern medical electronics is also one such field that relies on IoT. Execution time, data security, power, and hardware utilization are the four significant problems that should be addressed in the data communication system between intelligent devices. Due to the risks in the implementation algorithm complexity, certain ciphers are unsuitable for IoT applications. In addition, IoT applications are also implemented on an embedded platform wherein computing resources and memory are limited in number. Here in the research work, a reliable lightweight encryption algorithm with PRESENT has been implemented as a hardware accelerator and optimized for medical IoT-embedded applications. The PRESENT cipher is a reliable, lightweight encryption algorithm in many applications. This paper presents a low latency 32-bit data path of PRESENT cipher architecture that provides high throughput. The proposed hardware architecture has been implemented and tested with XILINX XC7Z030FBG676-2 ZYNQ FPGA board 7000. This work shows an improvement of about 85.54% in throughput with a reasonable trade-off over hardware utilization.<\/jats:p>","DOI":"10.3390\/cryptography7010006","type":"journal-article","created":{"date-parts":[[2023,2,6]],"date-time":"2023-02-06T04:59:10Z","timestamp":1675659550000},"page":"6","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":12,"title":["High Throughput PRESENT Cipher Hardware Architecture for the Medical IoT Applications"],"prefix":"10.3390","volume":"7","author":[{"given":"Jamunarani","family":"Damodharan","sequence":"first","affiliation":[{"name":"Faculty of Electronics Engineering, Sathyabama Institute of Science and Technology, Chennai 600119, India"}]},{"given":"Emalda Roslin","family":"Susai Michael","sequence":"additional","affiliation":[{"name":"Department of Electronics and Communication Engineering, Sathyabama Institute of Science and Technology, Chennai 600119, India"}]},{"given":"Nasir","family":"Shaikh-Husin","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, Universiti Teknologi Malaysia, Johor Bahru 81310, Malaysia"}]}],"member":"1968","published-online":{"date-parts":[[2023,2,6]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"103906","DOI":"10.1109\/ACCESS.2021.3094024","article-title":"Design and Development of Deep Learning-Based Model for Anomaly Detection in IoT Networks","volume":"9","author":"Ullah","year":"2021","journal-title":"IEEE Access"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"682","DOI":"10.1080\/00051144.2020.1816388","article-title":"FPGA implementation of hardware architecture with AES encryptor using sub-pipelined S-box techniques for compact applications","volume":"61","year":"2020","journal-title":"Automatika"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1109\/TVLSI.2015.2391274","article-title":"A high-speed FPGA implementation of an RSD-based ECC processor","volume":"24","author":"Marzouqi","year":"2015","journal-title":"IEEE Trans. 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