{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T01:00:42Z","timestamp":1760144442991,"version":"build-2065373602"},"reference-count":25,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2024,4,22]],"date-time":"2024-04-22T00:00:00Z","timestamp":1713744000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>Recent evaluations of counter-based periodic testing strategies for fault detection in Microprocessor (\u03bcP) have shown that only a small set of counters is needed to provide complete coverage of severe faults. Severe faults are defined as faults that leak sensitive information, e.g., an encryption key on the output of a serial port. Alternatively, fault detection can be accomplished by executing instructions that periodically test the control and functional units of the \u03bcP. In this paper, we propose a fault detection method that utilizes an \u2019engineered\u2019 executable program combined with a small set of strategically placed counters in pursuit of a hardware Periodic Built-In-Self-Test (PBIST). We analyze two distinct methods for generating such a binary; the first uses an Automatic Test Generation Pattern (ATPG)-based methodology, and the second uses a process whereby existing counter-based node-monitoring infrastructure is utilized. We show that complete fault coverage of all leakage faults is possible using relatively small binaries with low latency to fault detection and by utilizing only a few strategically placed counters in the \u03bcP.<\/jats:p>","DOI":"10.3390\/cryptography8020016","type":"journal-article","created":{"date-parts":[[2024,4,22]],"date-time":"2024-04-22T07:44:09Z","timestamp":1713771849000},"page":"16","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor"],"prefix":"10.3390","volume":"8","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-3984-197X","authenticated-orcid":false,"given":"Idris O.","family":"Somoye","sequence":"first","affiliation":[{"name":"Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1876-117X","authenticated-orcid":false,"given":"Jim","family":"Plusquellic","sequence":"additional","affiliation":[{"name":"Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1051-473X","authenticated-orcid":false,"given":"Tom J.","family":"Mannos","sequence":"additional","affiliation":[{"name":"Advanced CMOS Products\/Design, Sandia National Laboratories, Albuquerque, NM 87131, USA"}]},{"given":"Brian","family":"Dziki","sequence":"additional","affiliation":[{"name":"Information Assurance Research, Department of Defense, Fort G. G. Meade, Fort Meade, MD 24003, USA"}]}],"member":"1968","published-online":{"date-parts":[[2024,4,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Yuce, B., Ghalaty, N.F., Deshpande, C., Patrick, C., Nazhandali, L., and Schaumont, P. (2016, January 18). FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response. Proceedings of the Hardware and Architectural Support for Security and Privacy 2016, HASP@ICSA 2016, Seoul, Republic of Korea.","DOI":"10.1145\/2948618.2948626"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Sere, A.A., Iguchi-Cartigny, J., and Lanet, J.L. (2009, January 15). Automatic Detection of Fault Attack and Countermeasures. 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