{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T01:17:17Z","timestamp":1760145437767,"version":"build-2065373602"},"reference-count":13,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2024,7,15]],"date-time":"2024-07-15T00:00:00Z","timestamp":1721001600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/100006234","name":"Sandia National Laboratories","doi-asserted-by":"publisher","award":["DE-NA-0003525"],"award-info":[{"award-number":["DE-NA-0003525"]}],"id":[{"id":"10.13039\/100006234","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.<\/jats:p>","DOI":"10.3390\/cryptography8030032","type":"journal-article","created":{"date-parts":[[2024,7,15]],"date-time":"2024-07-15T12:44:36Z","timestamp":1721047476000},"page":"32","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions"],"prefix":"10.3390","volume":"8","author":[{"given":"Jenilee","family":"Jao","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"given":"Ian","family":"Wilcox","sequence":"additional","affiliation":[{"name":"Radiation Modeling & Analysis, Sandia National Laboratories, Albuquerque, NM 87123, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1876-117X","authenticated-orcid":false,"given":"Jim","family":"Plusquellic","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, University of New Mexico, Albuquerque, NM 87131, USA"}]},{"given":"Biliana","family":"Paskaleva","sequence":"additional","affiliation":[{"name":"Radiation Modeling & Analysis, Sandia National Laboratories, Albuquerque, NM 87123, USA"}]},{"given":"Pavel","family":"Bochev","sequence":"additional","affiliation":[{"name":"Center for Computing Research, Sandia National Laboratories, Albuquerque, NM 87123, USA"}]}],"member":"1968","published-online":{"date-parts":[[2024,7,15]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"110","DOI":"10.1007\/s41635-023-00137-z","article-title":"An Analysis of FPGA LUT Bias and Entropy for Physical Unclonable Functions","volume":"7","author":"Jao","year":"2023","journal-title":"J. Hardw. Syst. Secur."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Bergeron, E., Feeley, M., Daigneault, M.A., and David, J.P. (2008, January 22\u201325). Using dynamic reconfiguration to implement high-resolution programmable delays on an FPGA. Proceedings of the 2008 Joint 6th International IEEE Northeast Workshop on Circuits and Systems and TAISA Conference, Montreal, QC, Canada.","DOI":"10.1109\/NEWCAS.2008.4606372"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1243","DOI":"10.1049\/iet-cds.2020.0026","article-title":"Fine resolution delay tuning method to improve the linearity of an unbalanced time-to-digital converter on a Xilinx FPGA","volume":"14","author":"Berrima","year":"2020","journal-title":"IET Circuits Devices Syst."},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Ruffoni, M., and Bogliolo, A. (2002, January 12\u201315). Direct Measures of Path Delays on Commercial FPGA Chips. Proceedings of the 6th IEEE Workshop on Signal Propagation on Interconnects, Pisa, Italy.","DOI":"10.1109\/SPI.2002.258304"},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Yu, H., Xu, Q., and Leong, P.H. (2010, January 8\u201310). Fine-grained characterization of process variation in FPGAs. Proceedings of the 2010 International Conference on Field-Programmable Technology, Beijing, China.","DOI":"10.1109\/FPT.2010.5681770"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Tuan, T., Lesea, A., Kingsley, C., and Trimberger, S. (2011, January 14\u201316). Analysis of within-die process variation in 65nm FPGAs. Proceedings of the 2011 12th International Symposium on Quality Electronic Design, Santa Clara, CA, USA.","DOI":"10.1109\/ISQED.2011.5770808"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3458843","article-title":"Process Variability Analysis in Interconnect, Logic, and Arithmetic Blocks of 16-Nm FinFET FPGAs","volume":"14","author":"Taka","year":"2021","journal-title":"ACM Trans. Reconfigurable Technol. Syst."},{"key":"ref_8","first-page":"639","article-title":"Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines","volume":"2014","author":"Majzoobi","year":"2014","journal-title":"IACR Cryptol. ePrint Arch."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Siecha, R.T., Alemu, G., Prinzie, J., and Leroux, P. (2023). 5.7 ps Resolution Time-to-Digital Converter Implementation Using Routing Path Delays. Electronics, 12.","DOI":"10.3390\/electronics12163478"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Sedcole, P., and Cheung, P.Y.K. (2006, January 13\u201315). Within-die delay variability in 90nm FPGAs and beyond. Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, Bangkok, Thailand.","DOI":"10.1109\/FPT.2006.270300"},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Cui, Y., Chen, Y., Wang, C., Gu, C., O\u2019Neill, M., and Liu, W. (2020, January 12\u201314). Programmable Ring Oscillator PUF Based on Switch Matrix. Proceedings of the 2020 IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain.","DOI":"10.1109\/ISCAS45731.2020.9180552"},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Owen, D., Heeger, D., Chan, C., Che, W., Saqib, F., Areno, M., and Plusquellic, J. (2018). An Autonomous, Self-Authenticating, and Self-Contained Secure Boot Process for Field-Programmable Gate Arrays. Cryptography, 2.","DOI":"10.3390\/cryptography2030015"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Plusquellic, J. (2022). Shift Register, Reconvergent-Fanout (SiRF) PUF Implementation on an FPGA. Cryptography, 6.","DOI":"10.3390\/cryptography6040059"}],"container-title":["Cryptography"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/2410-387X\/8\/3\/32\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,10]],"date-time":"2025-10-10T15:17:08Z","timestamp":1760109428000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/2410-387X\/8\/3\/32"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,15]]},"references-count":13,"journal-issue":{"issue":"3","published-online":{"date-parts":[[2024,9]]}},"alternative-id":["cryptography8030032"],"URL":"https:\/\/doi.org\/10.3390\/cryptography8030032","relation":{},"ISSN":["2410-387X"],"issn-type":[{"type":"electronic","value":"2410-387X"}],"subject":[],"published":{"date-parts":[[2024,7,15]]}}}