{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,22]],"date-time":"2026-07-22T16:42:46Z","timestamp":1784738566952,"version":"3.55.0"},"reference-count":24,"publisher":"MDPI AG","issue":"4","license":[{"start":{"date-parts":[[2025,12,1]],"date-time":"2025-12-01T00:00:00Z","timestamp":1764547200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100000836","name":"University of Liverpool","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100000836","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Cryptography"],"abstract":"<jats:p>As embedded and IoT systems demand secure and compact encryption, developing cryptographic solutions that are both lightweight and efficient remains a major challenge. Many existing AES implementations either lack flexibility or consume excessive hardware resources. This paper presents an area-efficient and flexible AES-128 implementation based on a hardware\/software (HW\/SW) co-design, specifically optimized for platforms with limited hardware resources, resulting in reduced power consumption. In this approach, key expansion is performed in software on a lightweight MicroBlaze processor, while encryption and decryption are accelerated by dedicated hardware IP cores optimized at the Look-up Table (LuT) level. The design is implemented on a Xilinx XC5VLX50T Virtex-5 FPGA, synthesized using Xilinx ISE 14.7, and tested at a 100 MHz system clock. It achieves a throughput of 13.3 Gbps and an area efficiency of 5.44 Gbps per slice, requiring only 2303 logic slices and 7 BRAMs on a Xilinx FPGA. It is particularly well-suited for resource-constrained applications such as IoT nodes, secure mobile devices, and smart cards. Since key expansion is executed only once per session, the runtime is dominated by AES core operations, enabling efficient processing of large data volumes. Although the present implementation targets AES-128, the HW\/SW partitioning allows straightforward extension to AES-192 and AES-256 by modifying only the software Key expansion module, ensuring practical scalability with no hardware changes. Moreover, the architecture offers a balanced trade-off between performance, flexibility and resource utilization without relying on complex pipelining. Experimental results demonstrate the effectiveness and flexibility of the proposed lightweight design.<\/jats:p>","DOI":"10.3390\/cryptography9040078","type":"journal-article","created":{"date-parts":[[2025,12,5]],"date-time":"2025-12-05T18:42:02Z","timestamp":1764960122000},"page":"78","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["Flexible and Area-Efficient Codesign Implementation of AES on FPGA"],"prefix":"10.3390","volume":"9","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7873-3832","authenticated-orcid":false,"given":"Oussama","family":"Azzouzi","sequence":"first","affiliation":[{"name":"Centre Universitaire El Cherif Bouchoucha Aflou, Aflou 03001, Algeria"},{"name":"Laboratory of System Design Methods, National Higher School of Computer Science, BP 68M, Algiers 16309, Algeria"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Mohamed","family":"Anane","sequence":"additional","affiliation":[{"name":"Laboratory of System Design Methods, National Higher School of Computer Science, BP 68M, Algiers 16309, Algeria"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7067-7848","authenticated-orcid":false,"given":"Mohamed Chahine","family":"Ghanem","sequence":"additional","affiliation":[{"name":"Cybersecurity Institute, School of Computer Science and Informatics, University of Liverpool, Liverpool L693BX, UK"},{"name":"Cyber Security Research Centre, London Metropolitan University, London N78DB, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8904-5587","authenticated-orcid":false,"given":"Yassine","family":"Himeur","sequence":"additional","affiliation":[{"name":"College of Engineering and Information Technology, University of Dubai, Dubai 14143, United Arab Emirates"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5560-0546","authenticated-orcid":false,"given":"Dominik","family":"Wojtczak","sequence":"additional","affiliation":[{"name":"Cybersecurity Institute, School of Computer Science and Informatics, University of Liverpool, Liverpool L693BX, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2025,12,1]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"944","DOI":"10.1007\/s11227-025-07390-9","article-title":"A secure and energy-efficient architecture in Internet of Things\u2013cloud computing network by enhancing and combining three cryptographic techniques via defining new features, areas, and entities","volume":"81","author":"Farshadinia","year":"2025","journal-title":"J. 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