{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,8,18]],"date-time":"2026-08-18T04:44:05Z","timestamp":1787028245211,"version":"3.56.0"},"reference-count":43,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2022,3,14]],"date-time":"2022-03-14T00:00:00Z","timestamp":1647216000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Nosh Technologies","award":["nosh\/agri-tech-000001"],"award-info":[{"award-number":["nosh\/agri-tech-000001"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Future Internet"],"abstract":"<jats:p>Most modern mobile cyber-physical systems such as smartphones come equipped with multi-processor systems-on-chip (MPSoCs) with variant computing capacity both to cater to performance requirements and reduce power consumption when executing an application. In this paper, we propose a novel approach to dynamic voltage and frequency scaling (DVFS) on CPU, GPU and RAM in a mobile MPSoC, which caters to the performance requirements of the executing application while consuming low power. We evaluate our methodology on a real hardware platform, Odroid XU4, and the experimental results prove the approach to be 26% more power-efficient and 21% more thermal-efficient compared to the state-of-the-art system.<\/jats:p>","DOI":"10.3390\/fi14030091","type":"journal-article","created":{"date-parts":[[2022,3,15]],"date-time":"2022-03-15T03:06:10Z","timestamp":1647313570000},"page":"91","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":15,"title":["CPU-GPU-Memory DVFS for Power-Efficient MPSoC in Mobile Cyber Physical Systems"],"prefix":"10.3390","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6161-4637","authenticated-orcid":false,"given":"Somdip","family":"Dey","sequence":"first","affiliation":[{"name":"School of Computer Science and Electronic Engineering (CSEE), University of Essex, Colchester CO4 3SQ, UK"},{"name":"Nosh Technologies, Colchester CO4 3SL, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Samuel","family":"Isuwa","sequence":"additional","affiliation":[{"name":"School of Electronics and Computer Science, University of Southampton, Southampton SO17 1BJ, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Suman","family":"Saha","sequence":"additional","affiliation":[{"name":"Nosh Technologies, Colchester CO4 3SL, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Amit Kumar","family":"Singh","sequence":"additional","affiliation":[{"name":"School of Computer Science and Electronic Engineering (CSEE), University of Essex, Colchester CO4 3SQ, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6412-8519","authenticated-orcid":false,"given":"Klaus","family":"McDonald-Maier","sequence":"additional","affiliation":[{"name":"School of Computer Science and Electronic Engineering (CSEE), University of Essex, Colchester CO4 3SQ, UK"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2022,3,14]]},"reference":[{"key":"ref_1","unstructured":"Cho, H.D., Engineer, P.D.P., Chung, K., and Kim, T. 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