{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,2]],"date-time":"2025-11-02T07:55:03Z","timestamp":1762070103040,"version":"build-2065373602"},"reference-count":45,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T00:00:00Z","timestamp":1665964800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100001863","name":"New Energy and Industrial Technology Development Organization (NEDO)","doi-asserted-by":"publisher","award":["JPNP16007"],"award-info":[{"award-number":["JPNP16007"]}],"id":[{"id":"10.13039\/501100001863","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Future Internet"],"abstract":"<jats:p>Hardware acceleration of cryptography algorithms represents an emerging approach to obtain benefits in terms of speed and side-channel resistance compared to software implementations. In addition, a hardware implementation can provide the possibility of unifying the functionality with some secure primitive, for example, a true random number generator (TRNG) or a physical unclonable function (PUF). This paper presents a unified PUF-ChaCha20 in a field-programmable gate-array (FPGA) implementation. The problems and solutions of the PUF implementation are described, exploiting the metastability in latches. The Xilinx Artix-7 XC7A100TCSG324-1 FPGA implementation occupies 2416 look-up tables (LUTs) and 1026 flips-flops (FFs), reporting a 3.11% area overhead. The PUF exhibits values of 49.15%, 47.52%, and 99.25% for the average uniformity, uniqueness, and reliability, respectively. Finally, ChaCha20 reports a speed of 0.343 cycles per bit with the unified implementation.<\/jats:p>","DOI":"10.3390\/fi14100298","type":"journal-article","created":{"date-parts":[[2022,10,17]],"date-time":"2022-10-17T05:08:02Z","timestamp":1665983282000},"page":"298","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["A Unified PUF and Crypto Core Exploiting the Metastability in Latches"],"prefix":"10.3390","volume":"14","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5501-0914","authenticated-orcid":false,"given":"Ronaldo","family":"Serrano","sequence":"first","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3746-8320","authenticated-orcid":false,"given":"Ckristian","family":"Duran","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3544-8839","authenticated-orcid":false,"given":"Marco","family":"Sarmiento","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2616-2510","authenticated-orcid":false,"given":"Tuan-Kiet","family":"Dang","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4078-0836","authenticated-orcid":false,"given":"Trong-Thuc","family":"Hoang","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5255-4919","authenticated-orcid":false,"given":"Cong-Kha","family":"Pham","sequence":"additional","affiliation":[{"name":"Department of Computer and Network Engineering, The University of Electro-Communications (UEC), Tokyo 182-8585, Japan"}]}],"member":"1968","published-online":{"date-parts":[[2022,10,17]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Kumar, V.B.Y., Chattopadhyay, A., Haj-Yahya, J., and Mendelson, A. (2019, January 3\u20136). ITUS: A Secure RISC-V System-on-Chip. Proceedings of the 32nd IEEE International System-on-Chip Conference (SOCC), Singapore.","DOI":"10.1109\/SOCC46988.2019.1570564307"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Nasahl, P., Schilling, R., Werner, M., and Mangard, S. (2021, January 7\u201311). HECTOR-V: A Heterogeneous CPU Architecture for a Secure RISC-V Execution Environment. Proceedings of the ACM Asia Conference on Computer and Communications Security (ASIA CCS), Virtual.","DOI":"10.1145\/3433210.3453112"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"46014","DOI":"10.1109\/ACCESS.2022.3169767","article-title":"Trusted Execution Environment Hardware by Isolated Heterogeneous Architecture for Key Scheduling","volume":"10","author":"Hoang","year":"2022","journal-title":"IEEE Access"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Taneja, S., Rajanna, V.K., and Alioto, M. (2021, January 13\u201322). 36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security. Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC42613.2021.9366019"},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"153","DOI":"10.1109\/JSSC.2021.3125255","article-title":"In-Memory Unified TRNG and Multi-Bit PUF for Ubiquitous Hardware Security","volume":"57","author":"Taneja","year":"2022","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"22311","DOI":"10.1109\/ACCESS.2022.3153359","article-title":"Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique","volume":"10","author":"Nam","year":"2022","journal-title":"IEEE Access"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"79213","DOI":"10.1109\/ACCESS.2022.3193639","article-title":"A Unified NVRAM and TRNG in Standard CMOS Technology","volume":"10","author":"Serrano","year":"2022","journal-title":"IEEE Access"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"963","DOI":"10.1109\/TED.2018.2792436","article-title":"True Random Number Generation Using Read Noise of Flash Memory Cells","volume":"65","author":"Ray","year":"2018","journal-title":"IEEE Trans. Electron Devices"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Ardila, J., Santamaria, J., Florez, K., and Roa, E. (2020, January 10\u201321). A Stable Physically Unclonable Function Based on a Standard CMOS NVR. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Sevilla, Spain.","DOI":"10.1109\/ISCAS45731.2020.9180411"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"3049","DOI":"10.1109\/JSSC.2021.3090247","article-title":"Fully Synthesizable Unified True Random Number Generator and Cryptographic Core","volume":"56","author":"Taneja","year":"2021","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Amaki, T., Hashimoto, M., and Onoye, T. (2011, January 15\u201318). An Oscillator-based True Random Number Generator with Jitter Amplifier. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil.","DOI":"10.1109\/ISCAS.2011.5937668"},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Peetermans, A., Rozic, V., and Verbauwhede, I. (2019, January 9\u201313). A Highly-Portable True Random Number Generator Based on Coherent Sampling. Proceedings of the 29th International Conference on Field Programmable Logic and Applications (FPL), Barcelona, Spain.","DOI":"10.1109\/FPL.2019.00041"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"2431","DOI":"10.1109\/TCAD.2021.3096464","article-title":"A Lightweight Full Entropy TRNG With On-Chip Entropy Assurance","volume":"40","author":"Chen","year":"2021","journal-title":"Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"281","DOI":"10.1049\/el.2014.0143","article-title":"Metastability occurrence based physical unclonable functions for FPGAs","volume":"50","author":"Wieczorek","year":"2014","journal-title":"Electron. Lett."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Yang, K., Fick, D., Henry, M.B., Lee, Y., Blaauw, D., and Sylvester, D. (2014, January 9\u201313). 16.3 A 23 Mb\/s 23 pJ\/b fully synthesized true-random-number generator in 28 nm and 65 nm CMOS. Proceedings of the IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2014.6757434"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Yang, K., Dong, Q., Blaauw, D., and Sylvester, D. (2015, January 22\u201326). 14.2 A physically unclonable function with BER < 10\u22128 for robust chip authentication using oscillator collapse in 40 nm CMOS. Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC) Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2015.7063022"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"41852","DOI":"10.1109\/ACCESS.2022.3167690","article-title":"A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse","volume":"10","author":"Serrano","year":"2022","journal-title":"IEEE Access"},{"key":"ref_18","first-page":"4058","article-title":"A PVT-Tolerant Oscillation-Collapse-Based True Random Number Generator with an Odd Number of Inverter Stages","volume":"69","author":"Park","year":"2022","journal-title":"IEEE Trans. Circuits Syst. Ii Express Briefs"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"105748","DOI":"10.1109\/ACCESS.2021.3099534","article-title":"A Fully Digital True Random Number Generator With Entropy Source Based in Frequency Collapse","volume":"9","author":"Serrano","year":"2021","journal-title":"IEEE Access"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"2807","DOI":"10.1109\/JSSC.2012.2217631","article-title":"2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors","volume":"47","author":"Mathew","year":"2012","journal-title":"IEEE J. Solid-State Circ."},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Torii, N., Yamamoto, D., and Matsumoto, T. (2016, January 28). Evaluation of Latch-Based Physical Random Number Generator Implementation on 40 Nm ASICs. Proceedings of the International Workshop on Trustworthy Embedded Devices (TrustED), Hofburg Palace, Vienna.","DOI":"10.1145\/2995289.2995292"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Tao, S., and Dubrova, E. (2017, January 22\u201324). TVL-TRNG: Sub-Microwatt True Random Number Generator Exploiting Metastability in Ternary Valued Latches. Proceedings of the IEEE International Symposium on Multiple-Valued Logic (ISMVL), Novi Sad, Serbia.","DOI":"10.1109\/ISMVL.2017.10"},{"key":"ref_23","doi-asserted-by":"crossref","unstructured":"Najm, Z., Jap, D., Jungk, B., Picek, S., and Bhasin, S. (2018, January 26\u201330). On Comparing Side-channel Properties of AES and ChaCha20 on Microcontrollers. Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Chengdu, China.","DOI":"10.1109\/APCCAS.2018.8605653"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Saraiva, D.A.F., Leithardt, V.R.Q., de Paula, D., Sales Mendes, A., Gonz\u00e1lez, G.V., and Crocker, P. (2019). PRISEC: Comparison of Symmetric Key Algorithms for IoT Devices. Sensors, 19.","DOI":"10.3390\/s19194312"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Darbar, S., Mervin, J., and Selvakumar, D. (2020, January 23\u201325). Side Channel Leakage Assessment Strategy On Attack Resistant AES Architectures. Proceedings of the 24th International Symposium on VLSI Design and Test (VDAT), Bhubaneswar, India.","DOI":"10.1109\/VDAT50263.2020.9190580"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"833","DOI":"10.1109\/OJCAS.2021.3127273","article-title":"ChaCha20-in-Memory for Side-Channel Resistance in IoT Edge-Node Devices","volume":"2","author":"Aamir","year":"2021","journal-title":"IEEE Open J. Circuits Syst."},{"key":"ref_27","doi-asserted-by":"crossref","unstructured":"Chou, Y.-H., and Lu, S.-L.L. (2019, January 22\u201325). A High Performance, Low Energy, Compact Masked 128-Bit AES in 22 nm CMOS Technology. Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Hsinchu, Taiwan.","DOI":"10.1109\/VLSI-DAT.2019.8741835"},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"945","DOI":"10.1109\/JSSC.2019.2960482","article-title":"A 4900-\u03bcm2 839-Mb\/s Side-Channel Attack-Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition","volume":"55","author":"Kumar","year":"2020","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Hong, Y.-L., Weng, Y.-K., and Huang, S.-H. (2021, January 15\u201317). Hardware Implementation for Fending off Side-Channel Attacks. Proceedings of the IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), Penghu, Taiwan.","DOI":"10.1109\/ICCE-TW52618.2021.9603186"},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Rescorla, E. (2018). The Transport Layer Security (TLS) Protocol Version 1.3, RFC Editor. RFC 8446.","DOI":"10.17487\/RFC8446"},{"key":"ref_31","doi-asserted-by":"crossref","unstructured":"Serrano, R., Duran, C., Hoang, T.-T., Sarmiento, M., Tsukamoto, A., Suzaki, K., and Pham, C.-K. (2021, January 6\u20139). ChaCha20-Poly1305 Crypto Core Compatible with Transport Layer Security 1.3. Proceedings of the International SoC Design Conference (ISOCC), Jeju Island, Korea.","DOI":"10.1109\/ISOCC53507.2021.9614016"},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Serrano, R., Duran, C., Sarmiento, M., Pham, C.K., and Hoang, T.T. (2022). ChaCha20-Poly1305 Authenticated Encryption with Additional Data for Transport Layer Security 1.3. Cryptography, 6.","DOI":"10.3390\/cryptography6020030"},{"key":"ref_33","unstructured":"Bernstein, D.J. (2008). The Salsa20 Family of Stream Ciphers. New Stream Cipher Designs: The eSTREAM Finalists, Springer."},{"key":"ref_34","unstructured":"Rescorla, E., and Dierks, T. (2008). The Transport Layer Security (TLS) Protocol Version 1.2, RFC Editor. RFC 5246."},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Nir, Y., and Langley, A. (2018). ChaCha20 and Poly1305 for IETF Protocols, RFC Editor. RFC 8439.","DOI":"10.17487\/RFC8439"},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"161427","DOI":"10.1109\/ACCESS.2020.3021205","article-title":"Configurable Ring Oscillator PUF Using Hybrid Logic Gates","volume":"8","author":"Deng","year":"2020","journal-title":"IEEE Access"},{"key":"ref_37","doi-asserted-by":"crossref","unstructured":"Garcia-Bosque, M., Aparicio, R., D\u00edez-Se\u00f1orans, G., S\u00e1nchez-Azqueta, C., and Celma, S. (2022, January 12\u201315). An analysis of the behaviour of a PUF based on ring oscillators depending on their locations. Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Villasimius, Italy.","DOI":"10.1109\/PRIME55000.2022.9816767"},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"27696","DOI":"10.1109\/ACCESS.2021.3058678","article-title":"Ultra-Low Power Oscillator Collapse Physical Unclonable Function Based on FinFET","volume":"9","author":"Zayed","year":"2021","journal-title":"IEEE Access"},{"key":"ref_39","doi-asserted-by":"crossref","first-page":"2208","DOI":"10.1109\/JSSC.2022.3157811","article-title":"A BER-Suppressed PUF with an Amplification of Process Mismatch Effect in an Oscillator Collapse Topology","volume":"57","author":"Park","year":"2022","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_40","unstructured":"Waterman, A., Lee, Y., Patterson, D.A., and Asanovi\u0107, K. (2016). The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1. Technical Report UCB\/EECS-2016-118, EECS Department, University of California."},{"key":"ref_41","doi-asserted-by":"crossref","unstructured":"Pfau, J., Reuter, M., Harbaum, T., Hofmann, K., and Becker, J. (2019, January 3\u20136). A Hardware Perspective on the ChaCha Ciphers: Scalable Chacha8\/12\/20 Implementations Ranging from 476 Slices to Bitrates of 175 Gbit\/s. Proceedings of the 32nd IEEE International System-on-Chip Conference (SOCC), Singapore.","DOI":"10.1109\/SOCC46988.2019.1570548289"},{"key":"ref_42","doi-asserted-by":"crossref","unstructured":"Athanas, P., Pnevmatikatos, D., and Sklavos, N. (2013). A Systematic Method to Evaluate and Compare the Performance of Physical Unclonable Functions. Embedded Systems Design with FPGAs, Springer.","DOI":"10.1007\/978-1-4614-1362-2"},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/3053681","article-title":"Improved Reliability of FPGA-Based PUF Identification Generator Design","volume":"10","author":"Gu","year":"2017","journal-title":"ACM Trans. Reconfigurable Technol. Syst."},{"key":"ref_44","doi-asserted-by":"crossref","first-page":"3566","DOI":"10.1109\/TCAD.2020.3012218","article-title":"Fast DRAM PUFs on Commodity Devices","volume":"39","author":"Jack","year":"2020","journal-title":"IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst."},{"key":"ref_45","doi-asserted-by":"crossref","first-page":"157830","DOI":"10.1109\/ACCESS.2020.3020020","article-title":"Proposal and Analysis of a Novel Class of PUFs Based on Galois Ring Oscillators","volume":"8","author":"Celma","year":"2020","journal-title":"IEEE Access"}],"container-title":["Future Internet"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1999-5903\/14\/10\/298\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T00:55:30Z","timestamp":1760144130000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1999-5903\/14\/10\/298"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,10,17]]},"references-count":45,"journal-issue":{"issue":"10","published-online":{"date-parts":[[2022,10]]}},"alternative-id":["fi14100298"],"URL":"https:\/\/doi.org\/10.3390\/fi14100298","relation":{},"ISSN":["1999-5903"],"issn-type":[{"type":"electronic","value":"1999-5903"}],"subject":[],"published":{"date-parts":[[2022,10,17]]}}}