{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,8]],"date-time":"2026-07-08T16:31:11Z","timestamp":1783528271795,"version":"3.55.0"},"reference-count":37,"publisher":"MDPI AG","issue":"8","license":[{"start":{"date-parts":[[2025,8,18]],"date-time":"2025-08-18T00:00:00Z","timestamp":1755475200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Information"],"abstract":"<jats:p>The need for efficient and real-time traffic sign recognition has become increasingly important as autonomous vehicles and Advanced Driver Assistance Systems (ADASs) continue to evolve. This study introduces TSRACE-AI, a system that accelerates traffic sign recognition by combining hardware and software in a hybrid architecture deployed on the PYNQ-Z2 FPGA platform. The design employs the Deep Learning Processing Unit (DPU) for hardware acceleration and incorporates 8-bit fixed-point quantization to enhance the performance of the CNN model. The proposed system achieves a 98.85% reduction in latency and a 200.28% increase in throughput compared to similar works, with a trade-off of a 90.35% decrease in power efficiency. Despite this trade-off, the system excels in latency-sensitive applications, demonstrating its suitability for real-time decision-making. By balancing speed and power efficiency, TSRACE-AI offers a compelling solution for integrating traffic sign recognition into ADAS, paving the way for enhanced autonomous driving capabilities.<\/jats:p>","DOI":"10.3390\/info16080703","type":"journal-article","created":{"date-parts":[[2025,8,19]],"date-time":"2025-08-19T07:56:06Z","timestamp":1755590166000},"page":"703","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["TSRACE-AI: Traffic Sign Recognition Accelerated with Co-Designed Edge AI Based on Hybrid FPGA Architecture for ADAS"],"prefix":"10.3390","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-2642-7807","authenticated-orcid":false,"given":"Abderrahmane","family":"Smaali","sequence":"first","affiliation":[{"name":"LAVETE Laboratory, National School of Applied Sciences of Berrechid, University of Hassan I, Settat 26000, Morocco"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Said","family":"Ben Alla","sequence":"additional","affiliation":[{"name":"LAVETE Laboratory, National School of Applied Sciences of Berrechid, University of Hassan I, Settat 26000, Morocco"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8891-180X","authenticated-orcid":false,"given":"Abdellah","family":"Touhafi","sequence":"additional","affiliation":[{"name":"Department of Engineering Sciences and Technology (INDI), Vrije Universiteit Brussel (VUB), 1050 Brussels, Belgium"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2025,8,18]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Levinson, J., Askel, J., Becker, J., Dolson, J., Held, D., Kammel, S., Kolter, J.Z., Langer, D., Pink, O., and Pratt, V. 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