{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,25]],"date-time":"2026-06-25T16:09:32Z","timestamp":1782403772793,"version":"3.54.5"},"reference-count":103,"publisher":"MDPI AG","issue":"12","license":[{"start":{"date-parts":[[2024,11,21]],"date-time":"2024-11-21T00:00:00Z","timestamp":1732147200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Imaging"],"abstract":"<jats:p>This review provides an in-depth analysis of current hardware acceleration approaches for image processing and neural network inference, focusing on key operations involved in these applications and the hardware platforms used to deploy them. We examine various solutions, including traditional CPU\u2013GPU systems, custom ASIC designs, and FPGA implementations, while also considering emerging low-power, resource-constrained devices.<\/jats:p>","DOI":"10.3390\/jimaging10120298","type":"journal-article","created":{"date-parts":[[2024,11,21]],"date-time":"2024-11-21T06:11:54Z","timestamp":1732169514000},"page":"298","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":23,"title":["Image Processing Hardware Acceleration\u2014A Review of Operations Involved and Current Hardware Approaches"],"prefix":"10.3390","volume":"10","author":[{"ORCID":"https:\/\/orcid.org\/0009-0004-2573-0509","authenticated-orcid":false,"given":"Costin-Emanuel","family":"Vasile","sequence":"first","affiliation":[{"name":"Department of Electronic Devices, Circuits and Architectures, National University of Science and Technology Politehnica Bucharest, 060042 Bucharest, Romania"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Andrei-Alexandru","family":"Ulm\u0103mei","sequence":"additional","affiliation":[{"name":"Department of Electronic Devices, Circuits and Architectures, National University of Science and Technology Politehnica Bucharest, 060042 Bucharest, Romania"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7111-6324","authenticated-orcid":false,"given":"C\u0103lin","family":"B\u00eer\u0103","sequence":"additional","affiliation":[{"name":"Department of Electronic Devices, Circuits and Architectures, National University of Science and Technology Politehnica Bucharest, 060042 Bucharest, Romania"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2024,11,21]]},"reference":[{"key":"ref_1","first-page":"84","article-title":"ImageNet Classification with Deep Convolutional Neural Networks","volume":"25","author":"Krizhevsky","year":"2012","journal-title":"Neural Inf. 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