{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,8]],"date-time":"2026-04-08T16:50:56Z","timestamp":1775667056491,"version":"3.50.1"},"reference-count":29,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2019,1,13]],"date-time":"2019-01-13T00:00:00Z","timestamp":1547337600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100000266","name":"Engineering and Physical Sciences Research Council","doi-asserted-by":"publisher","award":["EP\/K009583\/1"],"award-info":[{"award-number":["EP\/K009583\/1"]}],"id":[{"id":"10.13039\/501100000266","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Imaging"],"abstract":"<jats:p>FPGA-based embedded image processing systems offer considerable computing resources but present programming challenges when compared to software systems. The paper describes an approach based on an FPGA-based soft processor called Image Processing Processor (IPPro) which can operate up to 337 MHz on a high-end Xilinx FPGA family and gives details of the dataflow-based programming environment. The approach is demonstrated for a k-means clustering operation and a traffic sign recognition application, both of which have been prototyped on an Avnet Zedboard that has Xilinx Zynq-7000 system-on-chip (SoC). A number of parallel dataflow mapping options were explored giving a speed-up of 8 times for the k-means clustering using 16 IPPro cores, and a speed-up of 9.6 times for the morphology filter operation of the traffic sign recognition using 16 IPPro cores compared to their equivalent ARM-based software implementations. We show that for k-means clustering, the 16 IPPro cores implementation is 57, 28 and 1.7 times more power efficient (fps\/W) than ARM Cortex-A7 CPU, nVIDIA GeForce GTX980 GPU and ARM Mali-T628 embedded GPU respectively.<\/jats:p>","DOI":"10.3390\/jimaging5010016","type":"journal-article","created":{"date-parts":[[2019,1,14]],"date-time":"2019-01-14T12:20:07Z","timestamp":1547468407000},"page":"16","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":47,"title":["FPGA-Based Processor Acceleration for Image Processing Applications"],"prefix":"10.3390","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4334-9478","authenticated-orcid":false,"given":"Fahad","family":"Siddiqui","sequence":"first","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sam","family":"Amiri","sequence":"additional","affiliation":[{"name":"School of Computing, Electronics and Maths, Coventry University, Coventry CV1 5FB, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9702-3070","authenticated-orcid":false,"given":"Umar Ibrahim","family":"Minhas","sequence":"additional","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tiantai","family":"Deng","sequence":"additional","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6201-4270","authenticated-orcid":false,"given":"Roger","family":"Woods","sequence":"additional","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Karen","family":"Rafferty","sequence":"additional","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Crookes","sequence":"additional","affiliation":[{"name":"School of Electronics, Electrical Engineering and Computer Science, Queen\u2019s University Belfast, Belfast BT7 1NN, UK"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2019,1,13]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"339","DOI":"10.1007\/s11265-015-1070-9","article-title":"PULP: A Ultra-Low Power Parallel Accelerator for Energy-Efficient and Flexible Embedded Vision","volume":"84","author":"Conti","year":"2016","journal-title":"J. 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