{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T16:52:57Z","timestamp":1777567977583,"version":"3.51.4"},"reference-count":15,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2019,3,6]],"date-time":"2019-03-06T00:00:00Z","timestamp":1551830400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee","doi-asserted-by":"publisher","award":["CRF C704716G"],"award-info":[{"award-number":["CRF C704716G"]}],"id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee","doi-asserted-by":"publisher","award":["GRF 17245716"],"award-info":[{"award-number":["GRF 17245716"]}],"id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002920","name":"Research Grants Council, University Grants Committee","doi-asserted-by":"publisher","award":["GRF 17203217"],"award-info":[{"award-number":["GRF 17203217"]}],"id":[{"id":"10.13039\/501100002920","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J. Imaging"],"abstract":"<jats:p>Parallel hardware designed for image processing promotes vision-guided intelligent applications. With the advantages of high-throughput and low-latency, streaming architecture on FPGA is especially attractive to real-time image processing. Notably, many real-world applications, such as region of interest (ROI) detection, demand the ability to process images continuously at different sizes and resolutions in hardware without interruptions. FPGA is especially suitable for implementation of such flexible streaming architecture, but most existing solutions require run-time reconfiguration, and hence cannot achieve seamless image size-switching. In this paper, we propose a dynamically-programmable buffer architecture (D-SWIM) based on the Stream-Windowing Interleaved Memory (SWIM) architecture to realize image processing on FPGA for image streams at arbitrary sizes defined at run time. D-SWIM redefines the way that on-chip memory is organized and controlled, and the hardware adapts to arbitrary image size with sub-100 ns delay that ensures minimum interruptions to the image processing at a high frame rate. Compared to the prior SWIM buffer for high-throughput scenarios, D-SWIM achieved dynamic programmability with only a slight overhead on logic resource usage, but saved up to     56 %     of the BRAM resource. The D-SWIM buffer achieves a max operating frequency of     329.5     MHz and reduction in power consumption by     45.7 %     comparing with the SWIM scheme. Real-world image processing applications, such as 2D-Convolution and the Harris Corner Detector, have also been used to evaluate D-SWIM\u2019s performance, where a pixel throughput of     4.5     Giga Pixel\/s and     4.2     Giga Pixel\/s were achieved respectively in each case. Compared to the implementation with prior streaming frameworks, the D-SWIM-based design not only realizes seamless image size-switching, but also improves hardware efficiency up to     30 \u00d7    .<\/jats:p>","DOI":"10.3390\/jimaging5030034","type":"journal-article","created":{"date-parts":[[2019,3,7]],"date-time":"2019-03-07T10:52:22Z","timestamp":1551955942000},"page":"34","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["High-Throughput Line Buffer Microarchitecture for Arbitrary Sized Streaming Image Processing"],"prefix":"10.3390","volume":"5","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4901-5476","authenticated-orcid":false,"given":"Runbin","family":"Shi","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, The University of Hong Kong, Pok Fu Lam, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4378-1199","authenticated-orcid":false,"given":"Justin S.J.","family":"Wong","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, The University of Hong Kong, Pok Fu Lam, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6514-0237","authenticated-orcid":false,"given":"Hayden K.-H.","family":"So","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, The University of Hong Kong, Pok Fu Lam, Hong Kong"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2019,3,6]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1690","DOI":"10.1109\/TITS.2014.2368980","article-title":"A multimodal ADAS system for unmarked urban scenarios based on road context understanding","volume":"16","author":"Guo","year":"2015","journal-title":"IEEE Trans. Intell. Transp. Syst."},{"key":"ref_2","unstructured":"Rosenfeld, A. (2013). Multiresolution Image Processing and Analysis, Springer Science & Business Media."},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Wang, M., Ng, H.C., Chung, B.M., Varma, B.S.C., Jaiswal, M.K., Tsia, K.K., Shum, H.C., and So, H.K.H. (2016, January 7\u20139). Real-time object detection and classification for high-speed asymmetric-detection time-stretch optical microscopy on FPGA. Proceedings of the 2016 International Conference on Field-Programmable Technology (FPT), Xi\u2019an, China.","DOI":"10.1109\/FPT.2016.7929548"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Ma, Y., Cao, Y., Vrudhula, S., and Seo, J.S. (2017, January 4\u20138). An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks. 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