{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T21:16:35Z","timestamp":1774386995944,"version":"3.50.1"},"reference-count":60,"publisher":"MDPI AG","issue":"19","license":[{"start":{"date-parts":[[2023,9,27]],"date-time":"2023-09-27T00:00:00Z","timestamp":1695772800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"National Key R &amp; D Program of China","award":["2022YFB3902304"],"award-info":[{"award-number":["2022YFB3902304"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Remote Sensing"],"abstract":"<jats:p>With the continuous development of satellite payload and system-on-chip (SoC) technology, spaceborne real-time synthetic aperture radar (SAR) imaging systems play a crucial role in various defense and civilian domains, including Earth remote sensing, military reconnaissance, disaster mitigation, and resource exploration. However, designing high-performance and high-reliability SAR imaging systems that operate in harsh environmental conditions while adhering to strict size, weight, and power consumption constraints remains a significant challenge. In this paper, we introduce a spaceborne SAR imaging chip based on a SoC architecture with system fault-tolerant technology. The fault-tolerant SAR SoC architecture has a CPU, interface subsystem, memory subsystem, data transit subsystem, and data processing subsystem. The data processing subsystem, which includes fast Fourier transform (FFT) modules, coordinated rotation digital computer (CORDIC) modules (for phase factor calculation), and complex multiplication modules, is the most critical component and can achieve various modes of SAR imaging. Through analyzing the computational requirements of various modes of SAR, we found that FFT accounted for over 50% of the total computational workload in SAR imaging processing, while the CORDIC modules for phase factor generation accounted for around 30%. Therefore, ensuring the fault tolerance of these two modules is crucial. To address this issue, we propose a word-length optimization redundancy (WLOR) method to make the fixed-point pipelined FFT processors in FFT modules fault tolerant. Additionally, we propose a fault-tolerant pipeline CORDIC architecture utilizing error correction code (ECC) and sum of squares (SOS) check. For other parts of the SoC architecture, we propose a generic partial triple modular redundancy (TMR) hardening method based on the HITS algorithm to improve fault tolerance. Finally, we developed a fully automated FPGA-based fault injection platform to test the design\u2019s effectiveness by injecting errors at arbitrary locations. The simulation results demonstrate that the proposed methods significantly improved the chip\u2019s fault tolerance, making the SAR imaging chip safer and more reliable. We also implemented a prototype measurement system with a chip-included board and demonstrated the proposed design\u2019s performance on the Chinese Gaofen-3 strip-map continuous imaging system. The chip requires 9.2 s, 50.6 s, and 7.4 s for a strip-map with 16,384 \u00d7 16,384 granularity, multi-channel strip-map with 65,536 \u00d7 8192 granularity, and multi-channel scan mode with 32,768 \u00d7 4096 granularity, respectively, and the system hardware consumes 6.9 W of power to process the SAR raw data.<\/jats:p>","DOI":"10.3390\/rs15194739","type":"journal-article","created":{"date-parts":[[2023,9,28]],"date-time":"2023-09-28T01:51:14Z","timestamp":1695865874000},"page":"4739","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":7,"title":["Advancements in Spaceborne Synthetic Aperture Radar Imaging with System-on-Chip Architecture and System Fault-Tolerant Technology"],"prefix":"10.3390","volume":"15","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4832-3453","authenticated-orcid":false,"given":"Yu","family":"Xie","sequence":"first","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China"}]},{"given":"Yizhuang","family":"Xie","sequence":"additional","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China"}]},{"given":"Bingyi","family":"Li","sequence":"additional","affiliation":[{"name":"Beijing Institute of Radio Measurement, Beijing 100854, China"}]},{"given":"He","family":"Chen","sequence":"additional","affiliation":[{"name":"Beijing Key Laboratory of Embedded Real-Time Information Processing Technology, Beijing Institute of Technology, Beijing 100081, China"}]}],"member":"1968","published-online":{"date-parts":[[2023,9,27]]},"reference":[{"key":"ref_1","unstructured":"Franceschetti, G., and Lanari, R. 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