{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,21]],"date-time":"2026-02-21T18:17:26Z","timestamp":1771697846532,"version":"3.50.1"},"reference-count":28,"publisher":"MDPI AG","issue":"3","license":[{"start":{"date-parts":[[2012,3,14]],"date-time":"2012-03-14T00:00:00Z","timestamp":1331683200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.<\/jats:p>","DOI":"10.3390\/s120303587","type":"journal-article","created":{"date-parts":[[2012,3,14]],"date-time":"2012-03-14T14:17:19Z","timestamp":1331734639000},"page":"3587-3604","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":69,"title":["A Voltage Mode Memristor Bridge Synaptic Circuit with Memristor Emulators"],"prefix":"10.3390","volume":"12","author":[{"given":"Maheshwar Pd.","family":"Sah","sequence":"first","affiliation":[{"name":"Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea"}]},{"given":"Changju","family":"Yang","sequence":"additional","affiliation":[{"name":"Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3321-5695","authenticated-orcid":false,"given":"Hyongsuk","family":"Kim","sequence":"additional","affiliation":[{"name":"Division of Electronics and Information Engineering, Chonbuk National University, Jeonju 561-756, Korea"}]},{"given":"Leon","family":"Chua","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering and Computer Sciences, University of California, Berkeley, CA 94720, USA"}]}],"member":"1968","published-online":{"date-parts":[[2012,3,14]]},"reference":[{"key":"ref_1","unstructured":"Haykin, S.S. Neural Networks: A Comprehensive Foundation, Prentice Hall."},{"key":"ref_2","first-page":"1075","article-title":"Introduction to neural networks","volume":"346","author":"Lawrence","year":"1995","journal-title":"CA Sci. Softw"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Rumelhart, D.E., and McClelland, J.L. (1986). Parallel Distributed Processing: Exploration in the Microstructure of Cognition, MIT Press.","DOI":"10.7551\/mitpress\/5236.001.0001"},{"key":"ref_4","unstructured":"Arbib, M.A. (1995). Handbook of Brain Research and Neural Network, MIT Press."},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Delagado-Frias, J.G., and Moore, W.R. (1991). VLSI for Artificial Intelligence and Neural Network, Plenum Publishing Company.","DOI":"10.1007\/978-1-4615-3752-6"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"333","DOI":"10.1142\/S0129065793000274","article-title":"Multiprocessor and memory architecture of the neurocomputers SYNAPSE-1","volume":"4","author":"Ramacher","year":"1993","journal-title":"Int. J. Neural Syst"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Holler, M., Tam, S., Castro, H., and Benson, R. (1989, January 18\u201322). An electrically trainable artificial neural network (ETANN) with 10240 \u201cFloating gate\u201d synapse. Washington, DC, USA.","DOI":"10.1109\/IJCNN.1989.118698"},{"key":"ref_8","unstructured":"Withagen, H. (July, January 27). Implementing backpropagation with analog hardware. Orlando, FL, USA."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"1194","DOI":"10.1117\/12.205116","article-title":"Survey of neural network hardware invited paper","volume":"2492","author":"Lindsey","year":"1995","journal-title":"Proc. Appl. Sci. Artif. Neural Networks Con"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"207","DOI":"10.1109\/4.50305","article-title":"Programmable analog vector-matrix multipliers","volume":"25","author":"Kub","year":"1990","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"403","DOI":"10.1109\/JETCAS.2011.2165755","article-title":"A highly dense, low power programmable analog vector-matrix multiplier: The FPAA implementation","volume":"1","author":"Schlottmann","year":"2011","journal-title":"IEEE J. Emer. Sel. Top. Circ. Syst"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"1273","DOI":"10.1109\/31.7601","article-title":"Cellular neural networks: Applications","volume":"35","author":"Chua","year":"1988","journal-title":"IEEE Trans. Circuits Syst"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"1257","DOI":"10.1109\/31.7600","article-title":"Cellular neural networks: Theory","volume":"35","author":"Chua","year":"1988","journal-title":"IEEE Trans. Circuits Syst"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"429","DOI":"10.1109\/TCSI.2003.808908","article-title":"Analog addition\/subtraction on the CNN-UM chip with short-time superimposition of input signals","volume":"50","author":"Kim","year":"2003","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"2208","DOI":"10.1109\/TCSI.2005.853263","article-title":"High-performance viterbi decoder with circularly connected 2-D CNN unilateral cell array","volume":"52","author":"Kim","year":"2005","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"1013","DOI":"10.1109\/4.597292","article-title":"A 0.8-\u03bcm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage","volume":"32","author":"Espejo","year":"1997","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"80","DOI":"10.1038\/nature06932","article-title":"The missing memristor found","volume":"453","author":"Strukov","year":"2008","journal-title":"Nature"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"507","DOI":"10.1109\/TCT.1971.1083337","article-title":"Memristor-the missing circuit element","volume":"CT-18","author":"Chua","year":"1971","journal-title":"IEEE Trans. Circuit Theory"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"209","DOI":"10.1109\/PROC.1976.10092","article-title":"Memristive devices and systems","volume":"64","author":"Chua","year":"1976","journal-title":"Proc. IEEE"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"1717","DOI":"10.1109\/JPROC.2009.2021077","article-title":"Circuit elements with memory: Memristor, memcapacitors and meminductors","volume":"97","author":"Ventra","year":"2009","journal-title":"Proc. IEEE"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"1066","DOI":"10.1109\/TNANO.2011.2105887","article-title":"Hebbian learning in spiking neural networks with nanocrystalline silicon TFTs and memristive synapse","volume":"10","author":"Cantley","year":"2011","journal-title":"IEEE Trans. Nanotechnol"},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1088\/0957-4484\/18\/36\/365202","article-title":"Self-organized computation with unreliable, memristive nanodevices","volume":"18","author":"Snider","year":"2007","journal-title":"Nanotechnology"},{"key":"ref_23","first-page":"148","article-title":"Neural synaptic weighting with a pulse-based memristor circuit","volume":"59","author":"Kim","year":"2011","journal-title":"IEEE Trans. Circuit Syst. I"},{"key":"ref_24","doi-asserted-by":"crossref","unstructured":"Kim, H., Sah, M.P, Yang, C, Roska, T, and Chua, L.O. (2012). Memristor bridge synapses. Proc. IEEE.","DOI":"10.1109\/JPROC.2011.2166749"},{"key":"ref_25","unstructured":"Kim, H., Sah, M.P, Yang, C, Cho, S., and Chua, L.O. (2012). Memristor emulator for memristor circuit applications. IEEE Trans. Circuit Syst. I, in press."},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"1857","DOI":"10.1109\/TCSI.2009.2038539","article-title":"Practical approach to programmable analog circuits with memristors","volume":"57","author":"Pershin","year":"2010","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"ref_27","unstructured":"Pershin, Y.V, and Ventra, M.D. ArXiv:0905.2935. Available online: http:\/\/arXiv.org\/abs\/arXiv:0905.2935 (accessed on 18 May 2009)."},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Yang, C., Sah, M.P., Adhikari, S., Park, D., and Kim, H. (2012). Highly accurate doublet generator for memristor-based analog memories. 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