{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,6]],"date-time":"2026-03-06T05:37:04Z","timestamp":1772775424226,"version":"3.50.1"},"reference-count":35,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2012,8,27]],"date-time":"2012-08-27T00:00:00Z","timestamp":1346025600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A novel k-winners-take-all (k-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing k-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other k-WTA CL counterparts operating with or without hardware support.<\/jats:p>","DOI":"10.3390\/s120911661","type":"journal-article","created":{"date-parts":[[2012,8,27]],"date-time":"2012-08-27T11:37:40Z","timestamp":1346067460000},"page":"11661-11683","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Efficient k-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning"],"prefix":"10.3390","volume":"12","author":[{"given":"Chien-Min","family":"Ou","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, Ching Yun University, Jhongli 320, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hui-Ya","family":"Li","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4003-1568","authenticated-orcid":false,"given":"Wen-Jyi","family":"Hwang","sequence":"additional","affiliation":[{"name":"Department of Computer Science and Information Engineering, National Taiwan Normal University, Taipei 116, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2012,8,27]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"949","DOI":"10.1109\/TCSI.2005.846662","article-title":"Stable computational dynamics for a class of circuits with O(N) interconnections capable of KWTA and rank extractions","volume":"52","author":"Marinov","year":"2005","journal-title":"IEEE Trans. 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