{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T22:13:55Z","timestamp":1760220835406,"version":"build-2065373602"},"reference-count":15,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2013,12,20]],"date-time":"2013-12-20T00:00:00Z","timestamp":1387497600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/3.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper presents a novel self-timed multi-purpose sensor especially conceived for Field Programmable Gate Arrays (FPGAs). The aim of the sensor is to measure performance variations during the life-cycle of the device, such as process variability, critical path timing and temperature variations. The proposed topology, through the use of both combinational and sequential FPGA elements, amplifies the time of a signal traversing a delay chain to produce a pulse whose width is the sensor\u2019s measurement. The sensor is fully self-timed, avoiding the need for clock distribution networks and eliminating the limitations imposed by the system clock. One single off- or on-chip time-to-digital converter is able to perform digitization of several sensors in a single operation. These features allow for a simplified approach for designers wanting to intertwine a multi-purpose sensor network with their application logic. Employed as a temperature sensor, it has been measured to have an error of  \u00b10.67 \u00b0C, over the range of 20\u2013100 \u00b0C, employing 20 logic elements with a 2-point calibration.<\/jats:p>","DOI":"10.3390\/s140100129","type":"journal-article","created":{"date-parts":[[2013,12,20]],"date-time":"2013-12-20T11:19:55Z","timestamp":1387538395000},"page":"129-143","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs)"],"prefix":"10.3390","volume":"14","author":[{"given":"Carlos","family":"Osuna","sequence":"first","affiliation":[{"name":"Dpto. de Ingenier\u00eda Electr\u00f3nica, ETSI Telecomunicaci\u00f3n, Universidad Polit\u00e9cnica de Madrid, Avenida Complutense 30, Madrid 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pablo","family":"Ituero","sequence":"additional","affiliation":[{"name":"Dpto. de Ingenier\u00eda Electr\u00f3nica, ETSI Telecomunicaci\u00f3n, Universidad Polit\u00e9cnica de Madrid, Avenida Complutense 30, Madrid 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3833-524X","authenticated-orcid":false,"given":"Marisa","family":"L\u00f3pez-Vallejo","sequence":"additional","affiliation":[{"name":"Dpto. de Ingenier\u00eda Electr\u00f3nica, ETSI Telecomunicaci\u00f3n, Universidad Polit\u00e9cnica de Madrid, Avenida Complutense 30, Madrid 28040, Spain"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2013,12,20]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Ghosh, S., and Roy, K. (2010). Parameter variation tolerance and error resiliency: New design paradigm for the nanoscale era. Proc. IEEE, 1718\u20131751.","DOI":"10.1109\/JPROC.2010.2057230"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Zick, K.M., and Hayes, J.P. (2012). Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems. ACM Trans. Reconfigurable Technol. Syst., 5.","DOI":"10.1145\/2133352.2133353"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1736","DOI":"10.1109\/JSEN.2011.2176485","article-title":"Light-weight on-chip monitoring network for dynamic adaptation and calibration","volume":"12","author":"Ituero","year":"2012","journal-title":"Sens. J. IEEE"},{"key":"ref_4","doi-asserted-by":"crossref","unstructured":"Long, J., Memik, S.O., Memik, G., and Mukherjee, R. (2008). Thermal monitoring mechanisms for chip multiprocessors. ACM Trans. Archit. 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Ipojuca, Brizal.","DOI":"10.1109\/SPL.2010.5483027"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Hung, E., Wilton, S., Yu, H., Chau, T., and Leong, P.H.W. (2009, January 9\u201311). A Detailed Delay Path Model for FPGAs. Sydney, Australia.","DOI":"10.1109\/FPT.2009.5377673"},{"key":"ref_10","unstructured":"Rabaey, J.M., Chandrakasan, A., and Nikolic, B. (2003). Digital Integrated Circuits, Prentice Hall."},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Sedcole, P., and Cheung, P.Y.K. (2006, January 13\u201315). Within-Die Delay Variability in 90nm FPGAs and Beyond. Bangkok, Thailand.","DOI":"10.1109\/FPT.2006.270300"},{"key":"ref_12","unstructured":"Masuda, H., Ohkawa, S., Kurokawa, A., and Aoki, M. (2005, January 18\u201321). Challenge: Variability Characterization and Modeling for 65- to 90-nm Processes. San Jose, CA, USA."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Friedberg, P., Cao, Y., Cain, J., Wang, R., Rabaey, J., and Spanos, C. (2005, January 21\u201323). Modeling Within-Die Spatial Correlation Effects for Process-Design Co-Optimization. Washington, DC, USA.","DOI":"10.1117\/12.600028"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Wolpert, D., and Ampadu, P. (2012). Managing Temperature Effects in Nanoscale Adaptive Systems, Springer.","DOI":"10.1007\/978-1-4614-0748-5"},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"G\u00f3mez-Osuna, C., S\u00e1nchez, M.A., Ituero, P., and L\u00f3pez-Vallejo, M. (2012, January 10\u201313). A Monitoring Infrastructure for FPGA Self-Awareness Dynamic Adaptation. Sevilla, Spain.","DOI":"10.1109\/ICECS.2012.6463547"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/14\/1\/129\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T21:51:33Z","timestamp":1760219493000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/14\/1\/129"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,12,20]]},"references-count":15,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2014,1]]}},"alternative-id":["s140100129"],"URL":"https:\/\/doi.org\/10.3390\/s140100129","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2013,12,20]]}}}