{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,28]],"date-time":"2026-01-28T11:27:03Z","timestamp":1769599623257,"version":"3.49.0"},"reference-count":38,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2014,9,29]],"date-time":"2014-09-29T00:00:00Z","timestamp":1411948800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.<\/jats:p>","DOI":"10.3390\/s141018223","type":"journal-article","created":{"date-parts":[[2014,9,29]],"date-time":"2014-09-29T11:16:45Z","timestamp":1411989405000},"page":"18223-18243","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":25,"title":["Parallel Fixed Point Implementation of a Radial Basis Function Network in an FPGA"],"prefix":"10.3390","volume":"14","author":[{"given":"Alisson","family":"De Souza","sequence":"first","affiliation":[{"name":"Department of Computer Engineering and Automation, Center of Technology, Federal University of Rio Grande do Norte\u2014UFRN, Natal 59078-970, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marcelo","family":"Fernandes","sequence":"additional","affiliation":[{"name":"Department of Computer Engineering and Automation, Center of Technology, Federal University of Rio Grande do Norte\u2014UFRN, Natal 59078-970, Brazil"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2014,9,29]]},"reference":[{"key":"ref_1","unstructured":"Haykin, S.S. (1999). Neural Networks: A Comprehensive Foundation, Prentice Hall. [2nd ed.]."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"240","DOI":"10.1109\/TNN.2006.883002","article-title":"The Impact of Arithmetic Representation on Implementing MLP-BP on FPGAs: A Study","volume":"18","author":"Savich","year":"2007","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"239","DOI":"10.1016\/j.neucom.2010.03.021","article-title":"Artificial neural networks in hardware: A survey of two decades of progress","volume":"74","author":"Misra","year":"2010","journal-title":"Neurocomputing"},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"945","DOI":"10.1016\/j.engappai.2004.08.011","article-title":"Artificial neural networks: A review of commercial hardware","volume":"17","author":"Dias","year":"2004","journal-title":"Eng. Appl. Artif. Intell."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"3848","DOI":"10.3390\/s130303848","article-title":"Efficient VLSI Architecture for Training Radial Basis Function Networks","volume":"13","author":"Fan","year":"2013","journal-title":"Sensors"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Latino, C., Moreno-Armendariz, M., and Hagan, M. (2009, January 14\u201319). Realizing general MLP networks with minimal FPGA resources. Atlanta, GA, USA.","DOI":"10.1109\/IJCNN.2009.5178680"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Hariprasath, S., and Prabakar, T.N. (2012, January 22\u201324). FPGA implementation of multilayer feed forward neural network architecture using VHDL. Dindigul, Tamilnadu, India.","DOI":"10.1109\/ICCCA.2012.6179225"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Hassan, A.A., Elnakib, A., and Abo-Elsoud, M. (2008, January 25\u201327). FPGA-based neuro-architecture intrusion detection system. Cairo, Egypt.","DOI":"10.1109\/ICCES.2008.4773010"},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Liddicoat, A.A., Slivovsky, L.A., McLenegan, T., and Heyer, D. (2006). FPGA-based artificial neural network using CORDIC modules. Proc. SPIE, 6313.","DOI":"10.1117\/12.682529"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"436","DOI":"10.1109\/TII.2011.2158843","article-title":"FPGA Implementation of the Multilayer Neural Network for the Speed Estimation of the Two-Mass Drive System","volume":"7","author":"Kaminski","year":"2011","journal-title":"IEEE Trans. Ind. Inform."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"320","DOI":"10.4236\/jsea.2011.45036","article-title":"FPGA Simulation of Linear and Nonlinear Support Vector Machine","volume":"4","author":"Mahmoodi","year":"2011","journal-title":"J. Softw. Eng. Appl."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Patra, J., Devi, T., and Meher, P. (2007, January 10\u201313). Radial basis function implementation of intelligent pressure sensor on field programmable gate array. Singapore.","DOI":"10.1109\/ICICS.2007.4449624"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Brassai, S., Bako, L., Pana, G., and Dan, S. (2008, January 22\u201324). Neural control based on RBF network implemented on FPGA. Brasov, Romania.","DOI":"10.1109\/OPTIM.2008.4602496"},{"key":"ref_14","unstructured":"Kim, J.S., and Jung, S. (2008, January 13\u201316). Evaluation of embedded RBF neural chip with back-propagation algorithm for pattern recognition tasks. Daejeon, Korea."},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Kung, Y.S., Wang, M.S., and Chuang, T.Y. (2009, January 5\u20138). FPGA-based self-tuning PID controller using RBF neural network and its application in X-Y table. Seoul, Korea.","DOI":"10.1109\/ISIE.2009.5214284"},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Seob Kim, J., and Jung, S. (2008, January 1\u20138). Implementation of the RBF neural chip with the on-line learning back-propagation algorithm. Hong Kong, China.","DOI":"10.1109\/IJCNN.2008.4633820"},{"key":"ref_17","unstructured":"Evert, P., Amudhan, R., and Paul, P. (2011, January 21\u201322). Implementation of neural network based controller using Verilog. Thuckafay, India."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Gargouri, A., Krid, M., and Masmoudi, D. (2010, January 27\u201330). Hardware implementation of pulse mode RBFNN based edge detection system on virtex V platform. Amman, Jordan.","DOI":"10.1109\/SSD.2010.5585520"},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Vizitiu, I.C., Rincu, I., Radu, A., Nicolaescu, I., and Popescu, F. (2010, January 20\u201322). Optimal FPGA implementation of GARBF systems. Basov, Ukraine.","DOI":"10.1109\/OPTIM.2010.5510449"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Kim, J.S., and Jung, S. (2009, January 5\u20138). Joint control of ROBOKER arm using a neural chip embedded on FPGA. Seoul, Korea.","DOI":"10.1109\/ISIE.2009.5221750"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"1162","DOI":"10.1109\/TNN.2003.816035","article-title":"Implementation of an RBF neural network on embedded systems: Real-time face tracking and identity verification","volume":"14","author":"Yang","year":"2003","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"134","DOI":"10.1016\/j.matcom.2012.05.006","article-title":"SOM neural network design\u2014A new Simulink library based approach targeting FPGA implementation","volume":"91","author":"Tisan","year":"2013","journal-title":"Math. Comput. Simul."},{"key":"ref_23","unstructured":"Xilinx System Generator User's Guide. Available online: http:\/\/www.xilinx.com."},{"key":"ref_24","unstructured":"Matlab\/Simulink Available online: http:\/\/www.mathworks.com."},{"key":"ref_25","unstructured":"Haykin, S.S. (1996). Adaptive Filter Theory, Prentice Hall. [3rd ed.]."},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Al-Kazzaz, S., and Khalil, R. (2008, January 7\u201311). FPGA Implementation of Artificial Neurons: Comparison study. Damascus, Syria.","DOI":"10.1109\/ICTTA.2008.4530261"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"1803","DOI":"10.1109\/TCAD.2007.896319","article-title":"Interconnect Criticality-Driven Delay Relaxation","volume":"26","author":"Singhal","year":"2007","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Dong, X., and Lemieux, G. (2009, January 9\u201311). PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. Sydney, Australia.","DOI":"10.1109\/FPT.2009.5377666"},{"key":"ref_29","unstructured":"Xilinx\u2014LogiCORE IP Multiplier V11.2\u2014Datasheet. Available online: http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/mult_gen_ds255.pdf."},{"key":"ref_30","unstructured":"Xilinx\u2014LogiCORE IP Adder\/Subtracter V11.0\u2014Datasheet. Available online: http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/addsub_ds214.pdf."},{"key":"ref_31","unstructured":"Xilinx\u2014LogiCORE IP Block Memory Generator v6.3\u2014Datasheet. Available online: http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/blk_mem_gen\/v6_3\/blk_mem_gen_ds512.pdf."},{"key":"ref_32","unstructured":"Xilinx\u2014LogiCORE IP Distributed Memory Generator v6.3\u2014Datasheet. Available online: http:\/\/www.xilinx.com\/support\/documentation\/ip_documentation\/dist_mem_gen\/v6_3\/dist_mem_gen_ds322.pdf."},{"key":"ref_33","unstructured":"Xilinx\u2014Virtex 6 FPGA DSP48E1 Slice\u2014User Guide. Available online: http:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug369.pdf."},{"key":"ref_34","doi-asserted-by":"crossref","unstructured":"Kilts, S. (2007). Advanced FPGA Design: Architecture, Implementation, and Optimization, Wiley.","DOI":"10.1002\/9780470127896"},{"key":"ref_35","doi-asserted-by":"crossref","first-page":"352","DOI":"10.1109\/TSMCC.2009.2038279","article-title":"Channel Equalization Using Neural Networks: A Review","volume":"40","author":"Burse","year":"2010","journal-title":"IEEE Trans. Syst. Man Cybern. Part C Appl. Rev."},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"2002","DOI":"10.1109\/TCOMM.2008.060004","article-title":"A nonlinear electrical equalizer with decision feedback for OOK optical communication systems","volume":"56","author":"Katz","year":"2008","journal-title":"IEEE Trans. Commun."},{"key":"ref_37","doi-asserted-by":"crossref","unstructured":"Cinar, E., and Sahin, F. (2009, January 2\u20134). EOG controlled mobile robot using Radial Basis Function Networks. Famagusta, Cyprus.","DOI":"10.1109\/ICSCCW.2009.5379485"},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"1235","DOI":"10.1109\/72.950152","article-title":"Efficient training of RBF neural networks for pattern recognition","volume":"12","author":"Lampariello","year":"2001","journal-title":"IEEE Trans. Neural Netw."}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/14\/10\/18223\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T21:16:29Z","timestamp":1760217389000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/14\/10\/18223"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,9,29]]},"references-count":38,"journal-issue":{"issue":"10","published-online":{"date-parts":[[2014,10]]}},"alternative-id":["s141018223"],"URL":"https:\/\/doi.org\/10.3390\/s141018223","relation":{},"ISSN":["1424-8220"],"issn-type":[{"value":"1424-8220","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,9,29]]}}}