{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:24:41Z","timestamp":1760243081196,"version":"build-2065373602"},"reference-count":34,"publisher":"MDPI AG","issue":"9","license":[{"start":{"date-parts":[[2015,9,4]],"date-time":"2015-09-04T00:00:00Z","timestamp":1441324800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"China National High Technologies Research Program","award":["2012AA012701"],"award-info":[{"award-number":["2012AA012701"]}]},{"name":"State Grid Cooperation of China","award":["SGRI-WD-71-13-014\/008\/010\/011"],"award-info":[{"award-number":["SGRI-WD-71-13-014\/008\/010\/011"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper proposes a real-time feature extraction VLSI architecture for  high-resolution images based on the accelerated KAZE algorithm. Firstly, a new system architecture is proposed. It increases the system throughput, provides flexibility in image resolution, and offers trade-offs between speed and scaling robustness. The architecture consists of a two-dimensional pipeline array that fully utilizes computational similarities in octaves. Secondly, a substructure (block-serial discrete-time cellular neural network) that can realize a nonlinear filter is proposed. This structure decreases the memory demand through the removal of data dependency. Thirdly, a hardware-friendly descriptor is introduced in order to overcome the hardware design bottleneck through the polar sample pattern; a simplified method to realize rotation invariance is also presented. Finally, the proposed architecture is designed in TSMC 65 nm CMOS technology. The experimental results show a performance of 127 fps in full HD resolution at 200 MHz frequency. The peak performance reaches 181 GOPS and the throughput is double the speed of other state-of-the-art architectures.<\/jats:p>","DOI":"10.3390\/s150922509","type":"journal-article","created":{"date-parts":[[2015,9,8]],"date-time":"2015-09-08T11:59:54Z","timestamp":1441713594000},"page":"22509-22529","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A 181 GOPS AKAZE Accelerator Employing Discrete-Time Cellular Neural Networks for Real-Time Feature Extraction"],"prefix":"10.3390","volume":"15","author":[{"given":"Guangli","family":"Jiang","sequence":"first","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Leibo","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenping","family":"Zhu","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shouyi","family":"Yin","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaojun","family":"Wei","sequence":"additional","affiliation":[{"name":"Institute of Microelectronics, Tsinghua University, Beijing 100084, China"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2015,9,4]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"1247","DOI":"10.1109\/JPROC.2003.814918","article-title":"Sensor networks: Evolution, opportunities, and challenges","volume":"91","author":"Chong","year":"2003","journal-title":"Proc. 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