{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:45:29Z","timestamp":1761648329221,"version":"build-2065373602"},"reference-count":22,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2016,1,30]],"date-time":"2016-01-30T00:00:00Z","timestamp":1454112000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 \u00b0C to 2.5 \u00b0C after one-point calibration in a range of \u221220 \u00b0C to 100 \u00b0C. The sensor consumed 95 \u03bcW using 1 kSa\/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.<\/jats:p>","DOI":"10.3390\/s16020176","type":"journal-article","created":{"date-parts":[[2016,2,1]],"date-time":"2016-02-01T10:03:26Z","timestamp":1454321006000},"page":"176","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":12,"title":["All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement"],"prefix":"10.3390","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-6354-0280","authenticated-orcid":false,"given":"Chun-Chi","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 81146, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3757-1400","authenticated-orcid":false,"given":"Chao-Lieh","family":"Chen","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 81146, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi","family":"Lin","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, National Kaohsiung First University of Science and Technology, Kaohsiung 81146, Taiwan"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2016,1,30]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Duarte, D.E., Geannopoulos, G., Mughal, U., Wong, K.L., and Taylor, G. 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