{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:21:09Z","timestamp":1760242869333,"version":"build-2065373602"},"reference-count":19,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2016,9,28]],"date-time":"2016-09-28T00:00:00Z","timestamp":1475020800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100004530","name":"Universiti Putra Malaysia","doi-asserted-by":"publisher","award":["GP-IPS\/2014\/9438713"],"award-info":[{"award-number":["GP-IPS\/2014\/9438713"]}],"id":[{"id":"10.13039\/501100004530","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>A Delay-Locked Loop (DLL) with a modified charge pump circuit is proposed for generating high-resolution linear delay steps with sub-picosecond jitter performance and adjustable delay range. The small-signal model of the modified charge pump circuit is analyzed to bring forth the relationship between the DLL\u2019s internal control voltage and output time delay. Circuit post-layout simulation shows that a 0.97 ps delay step within a 69 ps delay range with 0.26 ps Root-Mean Square (RMS) jitter performance is achievable using a standard 0.13 \u00b5m Complementary Metal-Oxide Semiconductor (CMOS) process. The post-layout simulation results show that the power consumption of the proposed DLL architecture\u2019s circuit is 0.1 mW when the DLL is operated at 2 GHz.<\/jats:p>","DOI":"10.3390\/s16101593","type":"journal-article","created":{"date-parts":[[2016,9,28]],"date-time":"2016-09-28T10:56:13Z","timestamp":1475060173000},"page":"1593","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Design of a Sub-Picosecond Jitter with Adjustable-Range CMOS Delay-Locked Loop for High-Speed and Low-Power Applications"],"prefix":"10.3390","volume":"16","author":[{"given":"Bilal","family":"Abdulrazzaq","sequence":"first","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"},{"name":"Department of Electronic and Communications Engineering, Al-Nahrain University, Al-Jadriya Complex, Baghdad 10070, Iraq"}]},{"given":"Omar","family":"Ibrahim","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"}]},{"given":"Shoji","family":"Kawahito","sequence":"additional","affiliation":[{"name":"Imaging Devices Laboratory, Research Institute of Electronics, Shizuoka University, 3-5-1 Johoku, Nakaku, Hamamatsu, Shizuoka 432-8011, Japan"}]},{"given":"Roslina","family":"Sidek","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"}]},{"given":"Suhaidi","family":"Shafie","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"}]},{"given":"Nurul","family":"Yunus","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"}]},{"given":"Lini","family":"Lee","sequence":"additional","affiliation":[{"name":"Faculty of Engineering, Multimedia University, Persiaran Multimedia, Cyberjaya 63100, Malaysia"}]},{"given":"Izhal","family":"Halin","sequence":"additional","affiliation":[{"name":"Department of Electrical and Electronic Engineering, Faculty of Engineering, Universiti Putra Malaysia, Serdang 43400, Selangor, Malaysia"}]}],"member":"1968","published-online":{"date-parts":[[2016,9,28]]},"reference":[{"key":"ref_1","unstructured":"Eto, S., Akita, H., Isobe, K., Tsuchida, K., Toda, H., and Seki, T. (2000, January 28\u201330). A 333 MHz, 20 mW, 18 ps resolution digital DLL using current-controlled delay with parallel variable resistor DAC (PVR-DAC). Proceedings of the Second IEEE Asia Pacific Conference on ASICs (AP-ASIC 2000), Cheju, Korea."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Seo, M.W., Kagawa, K., Yasutomi, K., Takasawa, T., Kawata, Y., Teranishi, N., Li, Z., Halin, I.A., and Kawahito, S. (2015, January 22\u201326). A 10.8 ps-time-resolution 256 \u00d7 512 image sensor with 2-Tap true-CDS lock-in pixels for fluorescence lifetime imaging. Proceedings of the 2015 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2015.7062994"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"557","DOI":"10.1109\/TCSI.2012.2215737","article-title":"A high-linearity, 17 ps precision time-to-digital converter based on a single-stage vernier delay loop fine interpolation","volume":"60","author":"Markovic","year":"2013","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"701","DOI":"10.1109\/TVLSI.2009.2036433","article-title":"A low power and wide range programmable clock generator with a high multiplication factor","volume":"19","author":"Jaehyouk","year":"2011","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2740963","article-title":"Robust and low-power digitally programmable delay element designs employing neuron-MOS mechanism","volume":"20","author":"Zhang","year":"2015","journal-title":"ACM Trans. Des. Autom. Electron. Syst."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"784","DOI":"10.1109\/4.918916","article-title":"A dual-loop delay-locked loop using multiple voltage-controlled delay lines","volume":"36","author":"Jung","year":"2001","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"661","DOI":"10.1109\/JSSC.2005.843596","article-title":"A wide-range and fast-locking all-digital cycle-controlled delay-locked loop","volume":"40","author":"Chang","year":"2005","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"662","DOI":"10.1109\/LMWC.2009.2029752","article-title":"A 0.6 V low-power wide-range delay-locked loop in 0.18 \u03bcm CMOS","volume":"19","author":"Lu","year":"2009","journal-title":"IEEE Microw. Wirel. Compon. Lett."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"561","DOI":"10.1109\/TCSII.2007.894413","article-title":"A fast-lock wide-range delay-locked loop using frequency-range selector for multiphase clock generator","volume":"54","author":"Cheng","year":"2007","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"6","DOI":"10.1109\/MCD.2005.1438751","article-title":"CMOS image sensors","volume":"21","author":"Eltoukhy","year":"2005","journal-title":"IEEE Circuits Devices Mag."},{"key":"ref_11","unstructured":"Maxim, A., Scott, B., Schneider, E., Hagge, M., Chacko, S., and Stiurca, D. (2001, January 6\u20139). Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. Proceedings of the 2001 IEEE International Symposium on Circuits and Systems (ISCAS 2001), Sydney, Australia."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"2338","DOI":"10.1109\/JSSC.2007.906183","article-title":"A 2.5 GHz all-digital delay-locked loop in 0.13 \u03bcm CMOS technology","volume":"42","author":"Yang","year":"2007","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"1036","DOI":"10.1109\/JSSC.2010.2047994","article-title":"A duty-cycle-distortion-tolerant half-delay-line low-power fast-lock-in all-digital delay-locked loop","volume":"45","author":"Wang","year":"2010","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"034703","DOI":"10.1063\/1.4868500","article-title":"A 7.5 ps single-shot precision integrated time counter with segmented delay line","volume":"85","author":"Klepacki","year":"2014","journal-title":"Rev. Sci. Instrum."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"2635","DOI":"10.1109\/JSSC.2015.2466443","article-title":"A wide-range, low-power, all-digital delay-locked loop with cyclic half-delay-line architecture","volume":"50","author":"Wang","year":"2015","journal-title":"IEEE J. Solid State Circuits"},{"key":"ref_16","unstructured":"Sedra, A.S., and Smith, K.C. (2004). Microelectronic Circuit, Oxford University Press. [5th ed.]."},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Baker, R.J. (2010). CMOS Circuit Design, Layout, and Simulation, Wiley-IEEE Press.","DOI":"10.1002\/9780470891179"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"555","DOI":"10.1109\/TCSII.2002.806248","article-title":"Low-jitter clock multiplication: A comparison between PLLs and DLLs","volume":"49","author":"Klumperink","year":"2002","journal-title":"IEEE Trans. Circuits Syst. II Analog Digit. Signal Process."},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"1286","DOI":"10.1109\/JSSC.2014.2319262","article-title":"A highly linear 1 GHz 1.3 dB NF CMOS low-noise amplifier with complementary transconductance linearization","volume":"49","author":"Kim","year":"2014","journal-title":"IEEE J. Solid State Circuits"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/16\/10\/1593\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T19:31:58Z","timestamp":1760211118000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/16\/10\/1593"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,9,28]]},"references-count":19,"journal-issue":{"issue":"10","published-online":{"date-parts":[[2016,10]]}},"alternative-id":["s16101593"],"URL":"https:\/\/doi.org\/10.3390\/s16101593","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2016,9,28]]}}}