{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:11:04Z","timestamp":1760242264172,"version":"build-2065373602"},"reference-count":22,"publisher":"MDPI AG","issue":"2","license":[{"start":{"date-parts":[[2017,2,22]],"date-time":"2017-02-22T00:00:00Z","timestamp":1487721600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"Ministry of Education, Korea","award":["NRF-2016R1D1A3B01015379"],"award-info":[{"award-number":["NRF-2016R1D1A3B01015379"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.<\/jats:p>","DOI":"10.3390\/s17020426","type":"journal-article","created":{"date-parts":[[2017,2,22]],"date-time":"2017-02-22T11:36:58Z","timestamp":1487763418000},"page":"426","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors"],"prefix":"10.3390","volume":"17","author":[{"given":"Seung-Ho","family":"Ok","sequence":"first","affiliation":[{"name":"Samsung Electronics, Hwaseong-si, Gyeonggi-do 18448, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yong-Hwan","family":"Lee","sequence":"additional","affiliation":[{"name":"School of Electronic Engineering, Kumoh National Institute of Technology, Gumi 39177, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jae","family":"Shim","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung","family":"Lim","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30332, USA"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8102-4818","authenticated-orcid":false,"given":"Byungin","family":"Moon","sequence":"additional","affiliation":[{"name":"School of Electronics Engineering, Kyungpook National University, Daegu 41566, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2017,2,22]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Szeliski, R. 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