{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T03:58:59Z","timestamp":1760241539087,"version":"build-2065373602"},"reference-count":21,"publisher":"MDPI AG","issue":"5","license":[{"start":{"date-parts":[[2018,4,24]],"date-time":"2018-04-24T00:00:00Z","timestamp":1524528000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>We have developed a high-speed vision chip using 3D stacking technology to address the increasing demand for high-speed vision chips in diverse applications. The chip comprises a 1\/3.2-inch, 1.27 Mpixel, 500 fps (0.31 Mpixel, 1000 fps, 2 \u00d7 2 binning) vision chip with 3D-stacked column-parallel Analog-to-Digital Converters (ADCs) and 140 Giga Operation per Second (GOPS) programmable Single Instruction Multiple Data (SIMD) column-parallel PEs for new sensing applications. The 3D-stacked structure and column parallel processing architecture achieve high sensitivity, high resolution, and high-accuracy object positioning.<\/jats:p>","DOI":"10.3390\/s18051313","type":"journal-article","created":{"date-parts":[[2018,4,25]],"date-time":"2018-04-25T03:22:45Z","timestamp":1524626565000},"page":"1313","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":19,"title":["Design and Performance of a 1 ms High-Speed Vision Chip with 3D-Stacked 140 GOPS Column-Parallel PEs \u2020"],"prefix":"10.3390","volume":"18","author":[{"given":"Atsushi","family":"Nose","sequence":"first","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Tomohiro","family":"Yamazaki","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Hironobu","family":"Katayama","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Shuji","family":"Uehara","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Masatsugu","family":"Kobayashi","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Sayaka","family":"Shida","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Masaki","family":"Odahara","sequence":"additional","affiliation":[{"name":"Sony LSI Design, Japan, 4-16-1 Okada, Atsugi-shi, Kanagawa 243-0021, Japan"}]},{"given":"Kenichi","family":"Takamiya","sequence":"additional","affiliation":[{"name":"Sony LSI Design, Japan, 4-16-1 Okada, Atsugi-shi, Kanagawa 243-0021, Japan"}]},{"given":"Shizunori","family":"Matsumoto","sequence":"additional","affiliation":[{"name":"Sony LSI Design, Japan, 4-16-1 Okada, Atsugi-shi, Kanagawa 243-0021, Japan"}]},{"given":"Leo","family":"Miyashita","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, 7 Chome-3-1 Hongo, Bunky\u014d, Tokyo 113-8654, Japan"}]},{"given":"Yoshihiro","family":"Watanabe","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, 7 Chome-3-1 Hongo, Bunky\u014d, Tokyo 113-8654, Japan"}]},{"given":"Takashi","family":"Izawa","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Yoshinori","family":"Muramatsu","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Yoshikazu","family":"Nitta","sequence":"additional","affiliation":[{"name":"Sony Semiconductor Solutions, Japan, 4-14-1 Asahi-cho, Atsugi-shi, Kanagawa 243-0014, Japan"}]},{"given":"Masatoshi","family":"Ishikawa","sequence":"additional","affiliation":[{"name":"Graduate School of Information Science and Technology, The University of Tokyo, 7 Chome-3-1 Hongo, Bunky\u014d, Tokyo 113-8654, Japan"}]}],"member":"1968","published-online":{"date-parts":[[2018,4,24]]},"reference":[{"key":"ref_1","unstructured":"Ishikawa, M., Ogawa, K., Komuro, T., and Ishii, I. (1999, January 17). A CMOS vision chip with SIMD processing element array for 1ms image processing. Proceedings of the 1999 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, CA, USA."},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"128","DOI":"10.1109\/JSSC.2014.2332134","article-title":"A 1000 fps Vision Chip Based on Dynamically Reconfigurable Hybrid Architecture Comprising a PE Array and Self-Organizing Map Neural Network","volume":"49","author":"Shi","year":"2014","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_3","doi-asserted-by":"crossref","unstructured":"Nakabo, Y., Ishikawa, M., Toyoda, H., and Mizuno, S. (2000, January 24\u201328). 1 ms Column Parallel Vision System and its Application of High Speed Target Tracking. Proceedings of the IEEE International Conference on Robotics and Automation, San Francisco, CA, USA.","DOI":"10.1109\/ROBOT.2000.844126"},{"key":"ref_4","first-page":"161","article-title":"Column-Parallel Architecture for Line-of-Sight Detection Image Sensor Based on Centroid Calculation","volume":"2","author":"Kawakami","year":"2014","journal-title":"ITE Trans. Media Technol. Appl."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"2333","DOI":"10.1109\/JSSC.2014.2342715","article-title":"A 240 \u00d7 180 130 dB 3 \u03bcs Latency Global Shutter Spatiotemporal Vision Sensor","volume":"49","author":"Brandli","year":"2014","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"566","DOI":"10.1109\/JSSC.2007.914337","article-title":"A 128 \u00d7 128 120 dB 15 \u03bcs Latency Asynchronous Temporal Contrast Vision Sensor","volume":"43","author":"Lichtsteiner","year":"2007","journal-title":"J. Solid-State Circuits"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"259","DOI":"10.1109\/JSSC.2010.2085952","article-title":"A QVGA 143 dB Dynamic Range Asynchronous Address-Event PWM Dynamic Image Sensor with Lossless Pixel-Level Video Compression","volume":"46","author":"Posch","year":"2011","journal-title":"J. Solid-State Circuits"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Son, B., Suh, Y., Kim, S., Jung, H., Kim, J.-S., Shin, C., Park, K., Lee, K., Park, J., and Woo, J. (2017, January 5\u20139). A 640 \u00d7 480 Dynamic Vision Sensor with a 9 \u03bcm Pixel and 300 Meps Address-Event Representation. Proceedings of the 2017 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2017.7870263"},{"key":"ref_9","first-page":"410","article-title":"A 1\/2.3-inch 10.3 Mpixel 50 frame\/s Back-Illuminated CMOS Image Sensor","volume":"53","author":"Wakabayashi","year":"2010","journal-title":"IEEE Int. Solid-State Circuits"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Toyama, T., Mishina, K., Tsuchiya, H., Ichikawa, T., Iwaki, H., Gendai, Y., Murakami, H., Takamiya, K., Shiroshita, H., and Muramatsu, Y. (2011, January 20\u201324). A 17.7 Mpixel 120 fps CMOS image sensor with 34.8 Gb\/s readout. Proceedings of the 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2011.5746379"},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Sakakibara, M., Oike, Y., Takatsuka, T., Kato, A., Honda, K., Taura, T., Machida, T., Okuno, J., Ando, A., and Fukuro, T. (2012, January 19\u201323). An 83 dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage. Proceedings of the 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2012.6177058"},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Hirayama, T. (2013, January 11\u201313). The evolution of CMOS image sensors. Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore.","DOI":"10.1109\/ASSCC.2013.6690968"},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Oike, Y., Akiyama, K., Hung, L.D., Niitsuma, W., Kato, A., Sato, M., Kato, Y., Nakamura, W., Shiroshita, H., and Sakano, Y. (2016, January 15\u201317). An 8.3 M-Pixel 480 fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure. Proceedings of the 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), Honolulu, HI, USA.","DOI":"10.1109\/VLSIC.2016.7573543"},{"key":"ref_14","doi-asserted-by":"crossref","unstructured":"Sukegawa, S., Umebayashi, T., Nakajima, T., Kawanobe, H., Koseki, K., Hirota, I., Haruta, T., Kasai, M., Fukumoto, K., and Wakano, T. (2013, January 17\u201321). A 1\/4-inch 8 Mpixel Back-Illuminated Stacked CMOS. Proceedings of the 2013 IEEE International Solid-State Circuits Conference, Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2013.6487825"},{"key":"ref_15","doi-asserted-by":"crossref","unstructured":"Yamazaki, T., Katayama, H., Uehara, S., Nose, A., Kobayashi, M., Shida, S., Odahara, M., Takamiya, K., Matsumoto, S., and Miyashita, L. (2017, January 5\u20139). A 1 ms High-Speed Vision Chip with 3D Stacked 140 GOPS Column Parallel PEs for Spatio-Temporal Image Processing. Proceedings of the 2017 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2017.7870271"},{"key":"ref_16","unstructured":"Kurokawa, M., Hashiguchi, A., Nakamura, K., Okuda, H., Aoyama, K., Yamazaki, T., Ohki, M., Soneda, M., Seno, K., and Kumata, I. (1996, January 10). 5.4 GOPS Linear Array Architecture DSP for Video\u2212Format Conversion. Proceedings of the 1996 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA."},{"key":"ref_17","unstructured":"Nakamura, K., Kurokawa, M., Hashiguchi, A., Kanou, M., Aoyama, K., Okuda, H., Iwase, S., and Yamazaki, T. (November, January 30). Video DSP architecture and its application design methodology for sampling rate conversion. Proceedings of the IEEE Workshop on VLSI Signal, San Francisco, CA, USA."},{"key":"ref_18","first-page":"661","article-title":"5.4 GOPS, 81 GB\/s Linear Array Architecture DSP","volume":"E81-C","author":"Hashiguchi","year":"1998","journal-title":"IEICE Trans. Electron."},{"key":"ref_19","unstructured":"Yamazaki, T., Nose, A., Katayama, H., Uehara, S., Kobayashi, M., Shida, S., Odahara, M., Takamiya, K., Hisamatsu, Y., and Matsumoto, S. (June, January 30). A 1 ms High-Speed Vision Chip with 3D Stacked 140 GOPS Column Parallel PEs for Diverse Sensing Applications. Proceedings of the 2017 International Image Sensor Workshop, Hiroshima, Japan."},{"key":"ref_20","unstructured":"Iwabuchi, S., Maruyama, Y., Ohgishi, Y., Muramatsu, M., Karasawa, N., and Hirayama, T. (2006, January 6\u20139). A Back-Illuminated High-Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal Wiring. Proceedings of the 2006 IEEE International Solid State Circuits Conference, San Francisco, CA, USA."},{"key":"ref_21","unstructured":"Ishii, I., and Ishikawa, M. (1999, January 10\u201315). Self-windowing for high speed vision. Proceedings of the 1999 IEEE International Conference on Robotics and Automation (Cat. No.99CH36288C), Detroit, MI, USA."}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/5\/1313\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T15:01:57Z","timestamp":1760194917000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/5\/1313"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,24]]},"references-count":21,"journal-issue":{"issue":"5","published-online":{"date-parts":[[2018,5]]}},"alternative-id":["s18051313"],"URL":"https:\/\/doi.org\/10.3390\/s18051313","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2018,4,24]]}}}