{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:01:53Z","timestamp":1760241713580,"version":"build-2065373602"},"reference-count":12,"publisher":"MDPI AG","issue":"8","license":[{"start":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T00:00:00Z","timestamp":1534464000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2016R1D1A1B04933413"],"award-info":[{"award-number":["2016R1D1A1B04933413"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003621","name":"Ministry of Science, ICT and Future Planning","doi-asserted-by":"publisher","award":["2016M3A7B4909668"],"award-info":[{"award-number":["2016M3A7B4909668"]}],"id":[{"id":"10.13039\/501100003621","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>We propose a dual-channel interface architecture that allocates high and low transition-density bit streams to two separate channels. The transmitter utilizes the stacked drivers with charge-recycling to reduce the power consumption. The direct current (DC)-coupled receiver front-end circuits manage the common-mode level variations and compensate for the channel loss. The tracked oversampling clock and data recovery (CDR), which realizes fast lock acquisition below 1 baud period and low logic latency, is shared by the two channels. Fabricated in a 65-nm low-power complementary metal-oxide semiconductor (CMOS) technology, the dual-channel transceiver achieves 12-Gb\/s data rate while the transmitter consumes 20.43 mW from a 1.2-V power supply.<\/jats:p>","DOI":"10.3390\/s18082709","type":"journal-article","created":{"date-parts":[[2018,8,17]],"date-time":"2018-08-17T10:54:25Z","timestamp":1534503265000},"page":"2709","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["A 12-Gb\/s Stacked Dual-Channel Interface for CMOS Image Sensor Systems"],"prefix":"10.3390","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9119-4530","authenticated-orcid":false,"given":"Sang-Hoon","family":"Kim","sequence":"first","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hoon","family":"Shin","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong 18448, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Youngkyun","family":"Jeong","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong 18448, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"June-Hee","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong 18448, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jaehyuk","family":"Choi","sequence":"additional","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jung-Hoon","family":"Chun","sequence":"additional","affiliation":[{"name":"College of Information and Communication Engineering, Sungkyunkwan University, Suwon 16419, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2018,8,17]]},"reference":[{"key":"ref_1","unstructured":"(2016, April 12). Specification Brief Physical Layers: M-PHY, D-PHY, C-PHY. Available online: http:\/\/mipi.org\/sites\/default\/files\/PHYTechBrief20140916.pdf."},{"key":"ref_2","unstructured":"(2016, April 12). Tektronix, C-PHY Essentials Transmitter Test Solution. Available online: http:\/\/www.tek.com\/sites\/tek.com\/files\/media\/media\/resources\/TekExpress-C-PHY-Tx-Datasheet-0.pdf."},{"key":"ref_3","unstructured":"(2016, April 12). Evolving CSI-2 Specification. Available online: https:\/\/www.mipi.org\/sites\/default\/files\/MIPICSI-2SpecificationBrief.pdf."},{"key":"ref_4","unstructured":"(2016, April 26). Caltech Image Database. Available online: http:\/\/www.vision.caltech.edu\/html-files\/archive.html."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"1438","DOI":"10.1109\/JSSC.2015.2420678","article-title":"An Energy\/Illumination-Adaptive CMOS Image Sensor with Reconfigurable Modes of Operations","volume":"50","author":"Choi","year":"2015","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_6","doi-asserted-by":"crossref","unstructured":"Lee, J.H., Kim, S.-H., Shin, J.S., Choi, D.C., Kwon, K.-W., and Chun, J.-H. (2013, January 4\u20137). A tracked oversampling digital data recovery for low latency, fast acquisition, and high jitter tolerance. Proceedings of the 2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS), Columbus, OH, USA.","DOI":"10.1109\/MWSCAS.2013.6674827"},{"key":"ref_7","unstructured":"Liu, Y., Hsieh, P.-H., Kim, S., Seo, J.-S., Montoye, R., Chang, L., Tierno, J., and Friedman, D. (2013, January 17\u201321). A 0.1pJ\/b 5-to-10Gb\/s charge-recycling stacked low-power I\/O for on-chip signaling in 45nm CMOS SOI. Proceedings of the 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, San Francisco, CA, USA."},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Kaviani, K., Amirkhany, A., Huang, C., Le, P., Madden, C., Saito, K., Sano, K., Murugan, V., Beyene, W., and Chang, K. (2012, January 19\u201323). A 0.4 mW\/Gb\/s 16 Gb\/s near-ground receiver front-end with replica transconductance termination calibration. Proceedings of the 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2012.6176950"},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"911","DOI":"10.1109\/JSSC.2012.2185369","article-title":"A 12.8-Gb\/s\/link Tri-Modal Single-Ended Memory Interface","volume":"47","author":"Amirkhany","year":"2012","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"3206","DOI":"10.1109\/JSSC.2013.2279053","article-title":"A 0.54 pJ\/b 20 Gb\/s Ground-Referenced Single-Ended Short-Reach Serial Link in 28 nm CMOS for Advanced Packaging Applications","volume":"48","author":"Poulton","year":"2013","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"2690","DOI":"10.1109\/JSSC.2016.2596773","article-title":"A 0.3 pJ\/bit 20 Gb\/s\/Wire Parallel Interface for Die-to-Die Communication","volume":"51","author":"Dehlaghi","year":"2016","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"1917","DOI":"10.1109\/JSSC.2015.2412688","article-title":"A 1.4 pJ\/bit, Power-Scalable 16x12 Gb\/s Source-Synchronous I\/O With DFE Receiver in 32 nm SOI CMOS Technology","volume":"50","author":"Dickson","year":"2015","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/8\/2709\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T15:19:22Z","timestamp":1760195962000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/8\/2709"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,8,17]]},"references-count":12,"journal-issue":{"issue":"8","published-online":{"date-parts":[[2018,8]]}},"alternative-id":["s18082709"],"URL":"https:\/\/doi.org\/10.3390\/s18082709","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2018,8,17]]}}}