{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,29]],"date-time":"2026-04-29T08:07:09Z","timestamp":1777450029019,"version":"3.51.4"},"reference-count":29,"publisher":"MDPI AG","issue":"10","license":[{"start":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T00:00:00Z","timestamp":1539648000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100003725","name":"National Research Foundation of Korea","doi-asserted-by":"publisher","award":["2018R1A2A2A05018621"],"award-info":[{"award-number":["2018R1A2A2A05018621"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error &lt;180 \u03bcV and the sampling error &lt;150 \u03bcV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 \u03bcm complementary metal\u2013oxide\u2013semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS\/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 \u03bcW at fS = 200 kS\/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ\/conversion-step.<\/jats:p>","DOI":"10.3390\/s18103486","type":"journal-article","created":{"date-parts":[[2018,10,16]],"date-time":"2018-10-16T11:07:51Z","timestamp":1539688071000},"page":"3486","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":4,"title":["A 1.15 \u03bcW 200 kS\/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques"],"prefix":"10.3390","volume":"18","author":[{"given":"Jae-Hun","family":"Lee","sequence":"first","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dasom","family":"Park","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Woojin","family":"Cho","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huu Nhan","family":"Phan","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Cong Luong","family":"Nguyen","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9160-2183","authenticated-orcid":false,"given":"Jong-Wook","family":"Lee","sequence":"additional","affiliation":[{"name":"School of Electronics and Information, Information and Communication System-on-Chip (SoC) Research Center, Kyung Hee University, Yongin 17104, Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2018,10,16]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"300","DOI":"10.1109\/JIOT.2014.2329189","article-title":"Design of a reconfigurable RFID sensing tag as a generic sensing platform toward the future internet of things","volume":"1","author":"Khan","year":"2014","journal-title":"IEEE Internet Things J."},{"key":"ref_2","unstructured":"Ginsburg, B., and Chandrakasen, A. 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