{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T04:08:20Z","timestamp":1760242100772,"version":"build-2065373602"},"reference-count":35,"publisher":"MDPI AG","issue":"12","license":[{"start":{"date-parts":[[2018,12,19]],"date-time":"2018-12-19T00:00:00Z","timestamp":1545177600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>The article presents novel hardware solutions for new intelligent sensors that can be used in wireless sensor networks (WSN). A substantial reduction of the amount of data sent by the sensor to the base station in the WSN may extend the possible sensor working time. Miniature integrated artificial neural networks (ANN) applied directly in the sensor can take over the analysis of data collected from the environment, thus reducing amount of data sent over the RF communication block. A prototype specialized chip with components of the ANN was designed in the CMOS 130 nm technology. An adaptation mechanism and a programmable multi-phase clock generator\u2014components of the ANN\u2014are described in more detail. Both simulation and measurement results of selected blocks are presented to demonstrate the correctness of the design.<\/jats:p>","DOI":"10.3390\/s18124499","type":"journal-article","created":{"date-parts":[[2018,12,19]],"date-time":"2018-12-19T12:12:44Z","timestamp":1545221564000},"page":"4499","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":8,"title":["Components of Artificial Neural Networks Realized in CMOS Technology to be Used in Intelligent Sensors in Wireless Sensor Networks"],"prefix":"10.3390","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7252-8013","authenticated-orcid":false,"given":"Tomasz","family":"Tala\u015bka","sequence":"first","affiliation":[{"name":"Faculty of Telecommunication, Computer Science and Electrical Engineering, UTP University of Science and Technology, 85-796 Bydgoszcz, Poland"},{"name":"Aptiv Services Poland S.A., 30-399 Krak\u00f3w, Poland"}]}],"member":"1968","published-online":{"date-parts":[[2018,12,19]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"5673","DOI":"10.1109\/ACCESS.2016.2598719","article-title":"Recent Advances in Energy-Efficient Routing Protocols for Wireless Sensor Networks: A Review","volume":"4","author":"Yan","year":"2016","journal-title":"IEEE Access"},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Srbinovska, M., Dimcev, V., and Gavrovski, C. (2017, January 6\u20138). Energy consumption estimation of wireless sensor networks in greenhouse crop production. Proceedings of the IEEE EUROCON 2017\u201317th International Conference on Smart Technologies, Ohrid, Macedonia.","DOI":"10.1109\/EUROCON.2017.8011235"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"2091","DOI":"10.1109\/TNN.2011.2169809","article-title":"Parallel programmable asynchronous neighborhood mechanism for Kohonen SOM implemented in CMOS technology","volume":"22","author":"Kolasa","year":"2011","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"961","DOI":"10.1109\/TNN.2010.2046497","article-title":"Realization of the conscience mechanism in CMOS implementation of winner-takes-all self-organizing neural networks","volume":"21","author":"Pedrycz","year":"2010","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"4731","DOI":"10.1109\/JSEN.2015.2442235","article-title":"Miniaturized Low-Power Wireless Sensor Interface","volume":"15","author":"Morrison","year":"2015","journal-title":"IEEE Sens. J."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"398","DOI":"10.1109\/JSYST.2009.2032440","article-title":"Wireless Body Sensor Network With Adaptive Low-Power Design for Biometrics and Healthcare Applications","volume":"3","author":"Chen","year":"2009","journal-title":"IEEE Syst. J."},{"key":"ref_7","unstructured":"Gao, D., and Fu, Y. (2010, January 15\u201317). A fully integrated SoC for large scale wireless sensor networks in 0.18 \u03bcm CMOS. Proceedings of the IET International Conference on Wireless Sensor Network (IET-WSN 2010), Beijing, China."},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/TII.2015.2423155","article-title":"Compact Low Power Wireless Gas Sensor Node With Thermo Compensation for Ubiquitous Deployment","volume":"11","author":"Somov","year":"2015","journal-title":"IEEE Trans. Ind. Inform."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"671","DOI":"10.3233\/THC-182514","article-title":"Novel techniques for a wireless motion capture system for the monitoring and rehabilitation of disabled persons for application in smart buildings","volume":"26","author":"Banach","year":"2018","journal-title":"J. Technol. Health Care"},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Banach, M., and D\u0142ugosz, R. (2017, January 9\u201311). Real-time Locating Systems for Smart City and Intelligent Transportation Applications. Proceedings of the IEEE 30th International Conference on Microelectronics (Miel 2017), Nis, Serbia.","DOI":"10.1109\/MIEL.2017.8190109"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"456","DOI":"10.1109\/72.217188","article-title":"Analog implementation of a Kohonen map with onchip learning","volume":"4","author":"Macq","year":"1993","journal-title":"IEEE Trans. Neural Netw."},{"key":"ref_12","unstructured":"Peiris, V. (2004). Mixed Analog Digital VLSI Implementation of a Kohonen Neural Network. [Ph.D. Thesis, D\u00e9pt. \u00c9lectr., Ecole Polytechnique F\u00e9d\u00e9rale Lausanne]."},{"key":"ref_13","first-page":"31","article-title":"Current-Mode Analog Adaptive Mechanism for Ultra-Low-Power Neural Networks","volume":"58","author":"Pedrycz","year":"2011","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"64","DOI":"10.1016\/j.mejo.2009.12.009","article-title":"Low power current-mode binary-tree asynchronous min\/max circuit","volume":"41","year":"2010","journal-title":"Microelectron. J."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"661","DOI":"10.1109\/TNNLS.2015.2434847","article-title":"Analog Programmable Distance Calculation Circuit for Winner Takes All Neural Network Realized in the CMOS Technology","volume":"27","author":"Kolasa","year":"2016","journal-title":"IEEE Trans. Neural Netw. Learn. Syst."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Kolasa, M., and D\u0142ugosz, R. (2015, January 25\u201327). An Advanced Software Model for Optimization of Self-Organizing Neural Networks Oriented on Implementation in Hardware. Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Torun, Poland.","DOI":"10.1109\/MIXDES.2015.7208524"},{"key":"ref_17","unstructured":"De Sousa, M.A., Pires, R., Perseghini, S., and Del-Moral-Hernandez, E. (2018, January 8\u201313). An FPGA-based SOM circuit architecture for online learning of 64-QAM data streams. Proceedings of the International Joint Conference on Neural Networks (IJCNN), Rio, Brazil."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Angelo de Abreu de Sousa, M., and Del-Moral-Hernandez, E. (2017, January 28\u201331). Comparison of three FPGA architectures for embedded multidimensional categorization through Kohonen\u2019s self-organizing maps. Proceedings of the International Symposium on Circuits and Systems (ISCAS), Baltimore, MD, USA.","DOI":"10.1109\/ISCAS.2017.8050799"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"153","DOI":"10.1109\/TCSVT.2014.2335831","article-title":"Novel FPGA Implementation of Hand Sign Recognition System With SOM\u2013Hebb Classifier","volume":"25","author":"Hikawa","year":"2015","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"key":"ref_20","unstructured":"D\u0142ugosz, R., Kolasa, M., and Szulc, M. (2011, January 16\u201318). A FPGA implementation of the asynchronous, programmable neighbourhood mechanism for WTM Self-Organizing Map. Proceedings of the International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gliwice, Poland."},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"1383","DOI":"10.1109\/JSSC.2004.831805","article-title":"A High-Speed and Low-Voltage Associative Co-Processor with Exact Hamming\/Manhattan-Distance Estimation Using Word-Parallel and Hierarchical Search Architecture","volume":"39","author":"Oike","year":"2004","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_22","doi-asserted-by":"crossref","unstructured":"Sasaki, S., Yasuda, M., and Mattausch, H.J. (2012, January 17\u201321). Digital Associative Memory for Word-Parrallel Manhattan-Distance-Based Vector Quantization. Proceedings of the European Solid-State Circuit conference (ESSCIRC 2012), Bordeaux, France.","DOI":"10.1109\/ESSCIRC.2012.6341289"},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"1448","DOI":"10.1109\/JSSC.2012.2190191","article-title":"Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping","volume":"47","author":"Mattausch","year":"2012","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"218","DOI":"10.1016\/j.amc.2017.02.030","article-title":"Analog, parallel, sorting circuit for the application in Neural Gas learning algorithm implemented in the CMOS technology","volume":"319","year":"2018","journal-title":"Appl. Math. Comput."},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"146","DOI":"10.1016\/j.neunet.2011.09.002","article-title":"A programmable triangular neighborhood function for a Kohonen self-organizing map implemented on chip","volume":"25","author":"Kolasa","year":"2012","journal-title":"Neural Netw."},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"D\u0142ugosz, R., Kolasa, M., Szulc, M., Pedrycz, W., and Farine, P.A. (2012, January 25\u201327). Implementation Issues of Kohonen Self-Organizing Map Realized on FPGA. Proceedings of the European Symposium on Artificial Neural Networks Advances in Computational Intelligence and Learning, Bruges, Belgium.","DOI":"10.1016\/j.neunet.2011.09.002"},{"key":"ref_27","doi-asserted-by":"crossref","unstructured":"Gao, X., Klumperink, E.A.M., and Nauta, B. (2007, January 27\u201330). Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers. Proceedings of the 2007 IEEE International Symposium on Circuits and Systems, New Orleans, LA, USA.","DOI":"10.1109\/ISCAS.2007.378767"},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"731","DOI":"10.1109\/JSSC.2010.2042254","article-title":"A 10-bit 50-MS\/s SAR ADC With a Monotonic Capacitor Switching Procedure","volume":"45","author":"Liu","year":"2010","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"D\u0142ugosz, R., Paw\u0142owski, P., and D\u0105browski, A. (2005, January 9\u201311). Multiphase clock generators with controlled clock impulse width for programmable high order rotator SC FIR filters realized in 0.35 \u03bcm CMOS technology. Proceedings of the Microtechnologies for the New Millennium 2005, Sevilla, Spain.","DOI":"10.1117\/12.608490"},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Shin, D., Koo, J., Yun, W.J., Choi, Y., and Kim, C. (2009, January 24\u201327). A fast-lock synchronous multiphase clock generator based on a time-to-digital converter. Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Taipei, Taiwan.","DOI":"10.1109\/ISCAS.2009.5117670"},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"015004","DOI":"10.1088\/1674-4926\/37\/1\/015004","article-title":"A 10 bit 50 MS\/s SAR ADC with partial split capacitor switching scheme in 0.18 \u03bcm CMOS","volume":"37","author":"Dong","year":"2016","journal-title":"J. Semiconduct."},{"key":"ref_32","doi-asserted-by":"crossref","unstructured":"Chuang, C.N., and Liu, S.I. (2007, January 11\u201315). A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology. Proceedings of the 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, Taipei, Taiwan.","DOI":"10.1109\/ISSCC.2007.373352"},{"key":"ref_33","unstructured":"Liu, T.-T., and Wang, C.-K. (2004, January 5). A 1\u20134 GHz DLL Based Low-Jitter Multi-Phase Clock Generator for Low-Band Ultra-Wideband Application. Proceedings of the IEEE Asia-Pacific Conference on Advanced System Integrated Circuits(AP-ASIC2004), Fukuoka, Japan."},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"2077","DOI":"10.1109\/JSSC.2006.880609","article-title":"A 120-MHz\u20131.8-GHz CMOS DLL-Based Clock Generator for Dynamic Frequency Scaling","volume":"41","author":"Kim","year":"2006","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_35","doi-asserted-by":"crossref","unstructured":"Kim, Y., Pham, P.-H., Heo, W., and Koo, J. (2009, January 22\u201324). A low-power programmable DLL-based clock generator with wide-range anti-harmonic lock. Proceedings of the International SoC Design Conference (ISOCC), Busan, Korea.","DOI":"10.1109\/SOCDC.2009.5423833"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/12\/4499\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T15:34:58Z","timestamp":1760196898000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/18\/12\/4499"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,12,19]]},"references-count":35,"journal-issue":{"issue":"12","published-online":{"date-parts":[[2018,12]]}},"alternative-id":["s18124499"],"URL":"https:\/\/doi.org\/10.3390\/s18124499","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2018,12,19]]}}}