{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,12]],"date-time":"2025-12-12T13:34:33Z","timestamp":1765546473540,"version":"build-2065373602"},"reference-count":35,"publisher":"MDPI AG","issue":"14","license":[{"start":{"date-parts":[[2019,7,11]],"date-time":"2019-07-11T00:00:00Z","timestamp":1562803200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Connected Component Analysis (CCA) plays an important role in several image analysis and pattern recognition algorithms. Being one of the most time-consuming tasks in such applications, specific hardware accelerator for the CCA are highly desirable. As its main characteristic, the design of such an accelerator must be able to complete a run-time process of the input image frame without suspending the input streaming data-flow, by using a reasonable amount of hardware resources. This paper presents a new approach that allows virtually any feature of interest to be extracted in a single-pass from the input image frames. The proposed method has been validated by a proper system hardware implemented in a complete heterogeneous design, within a Xilinx Zynq-7000 Field Programmable Gate Array (FPGA) System on Chip (SoC) device. For processing 640 \u00d7 480 input image resolution, only 760 LUTs and 787 FFs were required. Moreover, a frame-rate of ~325 fps and a throughput of 95.37 Mp\/s were achieved. When compared to several recent competitors, the proposed design exhibits the most favorable performance-resources trade-off.<\/jats:p>","DOI":"10.3390\/s19143055","type":"journal-article","created":{"date-parts":[[2019,7,11]],"date-time":"2019-07-11T11:28:28Z","timestamp":1562844508000},"page":"3055","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":17,"title":["An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis"],"prefix":"10.3390","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-2197-4563","authenticated-orcid":false,"given":"Fanny","family":"Spagnolo","sequence":"first","affiliation":[{"name":"Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, 87036 Rende, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1363-9201","authenticated-orcid":false,"given":"Stefania","family":"Perri","sequence":"additional","affiliation":[{"name":"Department of Mechanical, Energy and Management Engineering, University of Calabria, 87036 Rende, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9528-1110","authenticated-orcid":false,"given":"Pasquale","family":"Corsonello","sequence":"additional","affiliation":[{"name":"Department of Informatics, Modeling, Electronics and System Engineering, University of Calabria, 87036 Rende, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2019,7,11]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Farhat, W., Faiedg, H., Souani, C., and Besbes, K. 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