{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T00:49:58Z","timestamp":1760402998468,"version":"build-2065373602"},"reference-count":37,"publisher":"MDPI AG","issue":"8","license":[{"start":{"date-parts":[[2020,4,24]],"date-time":"2020-04-24T00:00:00Z","timestamp":1587686400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"DOI":"10.13039\/501100002460","name":"Chung-Ang University","doi-asserted-by":"publisher","award":["Graduate Research Scholarship in 2018"],"award-info":[{"award-number":["Graduate Research Scholarship in 2018"]}],"id":[{"id":"10.13039\/501100002460","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>Ultra-wideband (UWB) wireless communication is prospering as a powerful partner of the Internet-of-things (IoT). Due to the ongoing development of UWB wireless communications, the demand for high-speed and medium resolution analog-to-digital converters (ADCs) continues to grow. The successive approximation register (SAR) ADCs are the most powerful candidate to meet these demands, attracting both industries and academia. In particular, recent time-interleaved SAR ADCs show that multi-giga sample per second (GS\/s) can be achieved by overcoming the challenges of high-speed implementation of existing SAR ADCs. However, there are still critical issues that need to be addressed before the time-interleaved SAR ADCs can be applied in real commercial applications. The most well-known problem is that the time-interleaved SAR ADC architecture requires multiple sub-ADCs, and the mismatches between these sub-ADCs can significantly degrade overall ADC performance. And one of the most difficult mismatches to solve is the sampling timing skew. Recently, research to solve this timing-skew problem has been intensively studied. In this paper, we focus on the cutting-edge timing-skew calibration technique using a window detector. Based on the pros and cons analysis of the existing techniques, we come up with an idea that increases the benefits of the window detector-based timing-skew calibration techniques and minimizes the power and area overheads. Finally, through the continuous development of this idea, we propose a timing-skew calibration technique using a comparator offset-based window detector. To demonstrate the effectiveness of the proposed technique, intensive works were performed, including the design of a 7-bit, 2.5 GS\/s 5-channel time-interleaved SAR ADC and various simulations, and the results prove excellent efficacy of signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) of 40.79 dB and 48.97 dB at Nyquist frequency, respectively, while the proposed window detector occupies only 6.5% of the total active area, and consumes 11% of the total power.<\/jats:p>","DOI":"10.3390\/s20082430","type":"journal-article","created":{"date-parts":[[2020,4,24]],"date-time":"2020-04-24T11:42:14Z","timestamp":1587728534000},"page":"2430","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":17,"title":["Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems"],"prefix":"10.3390","volume":"20","author":[{"given":"Kiho","family":"Seong","sequence":"first","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Dong-Kyu","family":"Jung","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Dong-Hyun","family":"Yoon","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Jae-Soub","family":"Han","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Ju-Eon","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Nanyang Technology University, Singapore 639798, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1779-1799","authenticated-orcid":false,"given":"Tony Tae-Hyoung","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Nanyang Technology University, Singapore 639798, Singapore"}]},{"given":"Woojoo","family":"Lee","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]},{"given":"Kwang-Hyun","family":"Baek","sequence":"additional","affiliation":[{"name":"School of Electrical and Electronics Engineering, Chung-Ang University, Seoul 06974, Korea"}]}],"member":"1968","published-online":{"date-parts":[[2020,4,24]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","first-page":"678","DOI":"10.1109\/ACCESS.2015.2437951","article-title":"The Internet of Things for Health Care: A Comprehensive Survey","volume":"3","author":"Islam","year":"2015","journal-title":"IEEE Access"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"5247","DOI":"10.1109\/ACCESS.2017.2689040","article-title":"Big IoT Data Analytics: Architecture, Opportunities, and Open Research Challenges","volume":"5","author":"Marjani","year":"2017","journal-title":"IEEE Access"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1758","DOI":"10.1109\/TCAD.2018.2859240","article-title":"TEI-ULP: Exploiting Body Biasing to Improve the TEI-Aware Ultralow Power Methods","volume":"38","author":"Lee","year":"2019","journal-title":"IEEE Trans. Comput. Aided Des. Integr. Circuits Syst."},{"key":"ref_4","doi-asserted-by":"crossref","first-page":"112617","DOI":"10.1109\/ACCESS.2019.2935259","article-title":"LW-DEM: Designing a Low Power Digital-to-Analog Converter Using Lightweight Dynamic Element Matching Technique","volume":"7","author":"Yoon","year":"2019","journal-title":"IEEE Access"},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Alpman, E., Lakdawala, H., Carley, L.R., and Soumyanath, K. (2009, January 8\u201312). A 1.1 V 50 mW 2.5 GS\/s 7b Time-Interleaved C-2C SAR ADC in 45 nm LP digital CMOS. Proceedings of the 2009 IEEE International Solid-State Circuits Conference-Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2009.4977315"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"707","DOI":"10.1109\/JSSC.2010.2042249","article-title":"A Background Self-Calibrated 6b 2.7 GS\/s ADC With Cascade-Calibrated Folding-Interpolating Architecture","volume":"45","author":"Nakajima","year":"2010","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Ku, I., Xu, Z., Kuan, Y., Wang, Y., and Chang, M.F. (2011, January 19\u201321). A 40-mW 7-bit 2.2-GS\/s time-interleaved subranging ADC for low-power gigabit wireless communications in 65-nm CMOS. Proceedings of the 2011 IEEE Custom Integrated Circuits Conference (CICC), San Jose, CA, USA.","DOI":"10.1109\/CICC.2011.6055328"},{"key":"ref_8","doi-asserted-by":"crossref","unstructured":"Sung, B., Lee, C., Kim, W., Kim, J., Hong, H., Oh, G., Lee, C., Choi, M., Park, H., and Ryu, S. (2013, January 11\u201313). A 6 bit 2 GS\/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration. Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), Singapore.","DOI":"10.1109\/ASSCC.2013.6691037"},{"key":"ref_9","first-page":"339","article-title":"A 6-bit 1-GS\/s Two-Step SAR ADC in 40-nm CMOS","volume":"61","author":"Tai","year":"2014","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_10","first-page":"999","article-title":"A 6-bit 1.3-GS\/s Ping-Pong Domino-SAR ADC in 55-nm CMOS","volume":"65","author":"Chung","year":"2018","journal-title":"IEEE Trans. Circuits Syst. II Express Briefs"},{"key":"ref_11","doi-asserted-by":"crossref","unstructured":"Park, S., Palaskas, Y., and Flynn, M.P. (2006, January 6\u20139). A 4GS\/s 4b Flash ADC in 0.18\/spl mu\/m CMOS. Proceedings of the 2006 IEEE International Solid State Circuits Conference-Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2006.1696296"},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Park, S., Palaskas, Y., Ravi, A., Bishop, R.E., and Flynn, M.P. (2006, January 10\u201313). A 3.5 GS\/s 5-b Flash ADC in 90 nm CMOS. Proceedings of the IEEE Custom Integrated Circuits Conference 2006, San Jose, CA, USA.","DOI":"10.1109\/CICC.2006.320890"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"2303","DOI":"10.1109\/JSSC.2008.2004326","article-title":"A 6-bit 3.5-GS\/s 0.9-V 98-mW Flash ADC in 90-nm CMOS","volume":"43","author":"Deguchi","year":"2008","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"838","DOI":"10.1109\/JSSC.2011.2108125","article-title":"A 12-GS\/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration","volume":"46","author":"Murmann","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_15","unstructured":"Dortz, N.L., Blanc, J., Simon, T., Verhaeren, S., Rouat, E., Urard, P., Tual, S.L., Goguet, D., Lelandais-Perrault, C., and Benabes, P. (2014, January 9\u201313). 22.5 A 1.62 GS\/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS. Proceedings of the 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, USA."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"2846","DOI":"10.1109\/JSSC.2014.2362851","article-title":"A 1 GS\/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration","volume":"49","author":"Lee","year":"2014","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_17","doi-asserted-by":"crossref","first-page":"1929","DOI":"10.1109\/TCSI.2015.2452372","article-title":"A 1.2 V 2.64 GS\/s 8 bit 39 mW Skew-Tolerant Time-interleaved SAR ADC in 40 nm Digital LP CMOS for 60 GHz WLAN","volume":"62","author":"Kundu","year":"2015","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_18","doi-asserted-by":"crossref","unstructured":"Lin, C., Wei, Y., and Lee, T. (February, January 31). 27.7 A 10 b 2.6 GS\/s time-interleaved SAR ADC with background timing-skew calibration. Proceedings of the 2016 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2016.7418110"},{"key":"ref_19","doi-asserted-by":"crossref","first-page":"2712","DOI":"10.1109\/JSSC.2017.2732732","article-title":"A 2-GS\/s 8-bit Time-Interleaved SAR ADC for Millimeter-Wave Pulsed Radar Baseband SoC","volume":"52","author":"Miki","year":"2017","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"2563","DOI":"10.1109\/JSSC.2017.2713523","article-title":"A 10-b 800-MS\/s Time-Interleaved SAR ADC With Fast Variance-Based Timing-Skew Calibration","volume":"52","author":"Song","year":"2017","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"2584","DOI":"10.1109\/JSSC.2018.2843360","article-title":"A Time-Interleaved 12-b 270-MS\/s SAR ADC With Virtual-Timing-Reference Timing-Skew Calibration Scheme","volume":"53","author":"Kang","year":"2018","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"481","DOI":"10.1109\/TVLSI.2018.2874772","article-title":"Accuracy-Enhanced Variance-Based Time-Skew Calibration Using SAR as Window Detector","volume":"27","author":"Liu","year":"2019","journal-title":"IEEE Trans. Very Large Scale Integr. Syst."},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"2876","DOI":"10.1109\/TCSI.2019.2907581","article-title":"A 10-b 600-MS\/s 2-Way Time-Interleaved SAR ADC With Mean Absolute Deviation-Based Background Timing-Skew Calibration","volume":"66","author":"Song","year":"2019","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"261","DOI":"10.1109\/81.915383","article-title":"Explicit analysis of channel mismatch effects in time-interleaved ADC systems","volume":"48","author":"Kurosawa","year":"2001","journal-title":"IEEE Trans. Circuits Syst. I Fundam. Theory Appl."},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"1806","DOI":"10.1109\/JSSC.2013.2258814","article-title":"Design Considerations for Interleaved ADCs","volume":"48","author":"Razavi","year":"2013","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"971","DOI":"10.1109\/JSSC.2013.2239005","article-title":"A 2.8 GS\/s 44.6 mW Time-Interleaved ADC Achieving 50.9 dB SNDR and 3 dB Effective Resolution Bandwidth of 1.5 GHz in 65 nm CMOS","volume":"48","author":"Stepanovic","year":"2013","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"1751","DOI":"10.1109\/JSSC.2014.2313571","article-title":"An 8 Bit 4 GS\/s 120 mW CMOS ADC","volume":"49","author":"Wei","year":"2014","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_28","doi-asserted-by":"crossref","unstructured":"Sung, B., Jo, D., Jang, I., Lee, D., You, Y., Lee, Y., Park, H., and Ryu, S. (2015, January 22\u201326). 26.4 A 21fJ\/conv-step 9 ENOB 1.6 GS\/S 2\u00d7 time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45 nm CMOS. Proceedings of the 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2015.7063127"},{"key":"ref_29","doi-asserted-by":"crossref","unstructured":"Wang, X., Li, F., and Wang, Z. (2016, January 22\u201325). A novel autocorrelation-based timing mismatch C alibration strategy in Time-Interleaved ADCs. Proceedings of the 2016 IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, QC, Canada.","DOI":"10.1109\/ISCAS.2016.7527540"},{"key":"ref_30","doi-asserted-by":"crossref","unstructured":"Song, J., and Sun, N. (2018, January 8\u201311). A 10-b 600-MS\/s 2-way time-interleaved SAR ADC with mean absolute deviation based background timing-skew calibration. Proceedings of the 2018 IEEE Custom Integrated Circuits Conference (CICC).","DOI":"10.1109\/CICC.2018.8357058"},{"key":"ref_31","doi-asserted-by":"crossref","first-page":"543","DOI":"10.1109\/JSSC.2014.2364833","article-title":"A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS\/s Nonbinary 2b\/Cycle SAR ADC","volume":"50","author":"Hong","year":"2015","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"862","DOI":"10.1109\/JSSC.2008.2012329","article-title":"A 32 mW 1.25 GS\/s 6b 2b\/Step SAR ADC in 0.13$\\ \\mu$m CMOS","volume":"44","author":"Cao","year":"2009","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"2763","DOI":"10.1109\/JSSC.2012.2214181","article-title":"An 8-b 400-MS\/s 2-b-Per-Cycle SAR ADC With Resistive DAC","volume":"47","author":"Wei","year":"2012","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_34","doi-asserted-by":"crossref","first-page":"287","DOI":"10.1109\/JSSC.1987.1052715","article-title":"A versatile building block: The CMOS differential difference amplifier","volume":"22","author":"Sackinger","year":"1987","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_35","unstructured":"Kuttner, F. (2002, January 7). A 1.2 V 10 b 20 MSample\/s non-binary successive approximation ADC in 0.13\/spl mu\/m CMOS. Proceedings of the 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315), San Francisco, CA, USA."},{"key":"ref_36","first-page":"12","article-title":"The StrongARM Latch [A Circuit for All Seasons]","volume":"7","author":"Razavi","year":"2015","journal-title":"IEEE Solid-State Circuits Mag."},{"key":"ref_37","doi-asserted-by":"crossref","first-page":"3011","DOI":"10.1109\/JSSC.2013.2278471","article-title":"A 10b\/12b 40 kS\/s SAR ADC With Data-Driven Noise Reduction Achieving up to 10.1b ENOB at 2.2 fJ\/Conversion-Step","volume":"48","author":"Harpe","year":"2013","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/20\/8\/2430\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,13]],"date-time":"2025-10-13T14:09:18Z","timestamp":1760364558000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/20\/8\/2430"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,4,24]]},"references-count":37,"journal-issue":{"issue":"8","published-online":{"date-parts":[[2020,4]]}},"alternative-id":["s20082430"],"URL":"https:\/\/doi.org\/10.3390\/s20082430","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2020,4,24]]}}}