{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,12]],"date-time":"2025-10-12T03:01:09Z","timestamp":1760238069704,"version":"build-2065373602"},"reference-count":26,"publisher":"MDPI AG","issue":"14","license":[{"start":{"date-parts":[[2020,7,19]],"date-time":"2020-07-19T00:00:00Z","timestamp":1595116800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>The design of a Phase-Locked Loop (PLL) to generate the clock reference for the new Spacefibre standard is presented in this paper. Spacefibre has been recently released by the European Space Agency (ESA) and supports up to 6.25 Gbps for on-board satellite communications. Taking as a starting point a rad-hard 6.25 GHz Voltage Controlled Oscillator in 65 nm technology, this work presents the design of the key blocks for an integrated PLL: a Triple Modular Redundancy Phase\/Frequency Detector, a Charge Pump, and a passive Loop Filter. The modeling activities carried out in an Advanced Design System have proven that the proposed PLL can be completely integrated on-chip, with a Loop Filter area consumption of only 6000 \u00b5m2 (considering the 65 nm technology). The design of active circuits has been carried out at the transistor level in a Cadence Virtuoso environment, implementing both system and layout rad-hard techniques, and different solutions are discussed in this paper. As a result, a compact (0.09 mm2), low power (10.24 mW), dead zone free and rad-hard PLL is obtained with a Phase Noise below \u221280 dBc\/Hz @ 1 MHz. A preliminary block view and floor plan of the test chip is also proposed.<\/jats:p>","DOI":"10.3390\/s20144013","type":"journal-article","created":{"date-parts":[[2020,7,20]],"date-time":"2020-07-20T10:59:38Z","timestamp":1595242778000},"page":"4013","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":11,"title":["Analysis and Design of Integrated Blocks for a 6.25 GHz Spacefibre PLL"],"prefix":"10.3390","volume":"20","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2975-3471","authenticated-orcid":false,"given":"Marco","family":"Mestice","sequence":"first","affiliation":[{"name":"Department of Information Engineering (DII), University of Pisa; via G. Caruso 16, 56122 Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bruno","family":"Neri","sequence":"additional","affiliation":[{"name":"Department of Information Engineering (DII), University of Pisa; via G. Caruso 16, 56122 Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gabriele","family":"Ciarpi","sequence":"additional","affiliation":[{"name":"Department of Information Engineering (DII), University of Pisa; via G. Caruso 16, 56122 Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergio","family":"Saponara","sequence":"additional","affiliation":[{"name":"Department of Information Engineering (DII), University of Pisa; via G. Caruso 16, 56122 Pisa, Italy"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"1968","published-online":{"date-parts":[[2020,7,19]]},"reference":[{"key":"ref_1","unstructured":"European Cooperation for Space Standard (2019). SpaceFibre\u2014Very High-Speed Serial Link, ECSS. ECSS-E-ST-50-11C."},{"key":"ref_2","doi-asserted-by":"crossref","unstructured":"Wang, F., and Agrawal, V.D. (2008, January 4\u20138). Single Event Upset: An Embedded Tutorial. Proceedings of the 21st International Conference on VLSI Design (VLSID 2008), Hyderabad, India.","DOI":"10.1109\/VLSI.2008.28"},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"1833","DOI":"10.1109\/TNS.2008.2001040","article-title":"Radiation Effects in MOS Oxides","volume":"55","author":"Schwank","year":"2008","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_4","unstructured":"Suparta, W., and Zulkeple, S.K. (2015). An Assessment of the Space Radiation Environment in a Near-Equatorial Low Earth Orbit Based on the RazakSAT-1 Satellite. arXiv."},{"key":"ref_5","doi-asserted-by":"crossref","first-page":"2933","DOI":"10.1109\/TNS.2010.2066287","article-title":"A Generalized Linear Model for Single Event Transient Propagation in Phase-Locked Loops","volume":"57","author":"Loveless","year":"2010","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"106","DOI":"10.1109\/TNS.2016.2623696","article-title":"Analysis of Single-Event Effects in a Radiation-Hardened Low-Jitter PLL Under Heavy Ion and Pulsed Laser Irradiation","volume":"64","author":"Chen","year":"2017","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_7","doi-asserted-by":"crossref","unstructured":"Chen, L., Wen, X., You, Y., Huang, D., Li, C., and Chen, J. (2012, January 5\u20138). A radiation-tolerant ring oscillator phase-locked loop in 0.13\u00b5m CMOS. Proceedings of the IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS) 2012, Boise, ID, USA.","DOI":"10.1109\/MWSCAS.2012.6291945"},{"key":"ref_8","doi-asserted-by":"crossref","first-page":"2012","DOI":"10.1109\/TNS.2007.908166","article-title":"A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS","volume":"54","author":"Loveless","year":"2007","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_9","doi-asserted-by":"crossref","unstructured":"Kumar, R., Karkala, V., Garg, R., Jindal, T., and Khatri, S.P. (2009, January 4\u20137). A radiation tolerant Phase Locked Loop design for digital electronics. Proceedings of the IEEE International Conference on Computer Design 2009, Lake Tahoe, CA, USA.","DOI":"10.1109\/ICCD.2009.5413108"},{"key":"ref_10","doi-asserted-by":"crossref","first-page":"C12058","DOI":"10.1088\/1748-0221\/11\/12\/C12058","article-title":"Recent progress of RD53 Collaboration towards next generation Pixel Read-Out Chip for HL-LHC","volume":"11","author":"Barbero","year":"2016","journal-title":"J. Instrum."},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1109\/TNS.2017.2764501","article-title":"A 2.56-GHz SEU Radiation Hard LC -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology","volume":"65","author":"Prinzie","year":"2018","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_12","doi-asserted-by":"crossref","first-page":"245","DOI":"10.1109\/TNS.2016.2616919","article-title":"Comparison of a 65 nm CMOS Ring- and LC-Oscillator Based PLL in Terms of TID and SEU Sensitivity","volume":"64","author":"Prinzie","year":"2017","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_13","doi-asserted-by":"crossref","unstructured":"Prinzie, J., Steyaert, M., Leroux, P., Christiansen, J., and Moreira, P. (2016, January 7\u20139). A single-event upset robust, 2.2 GHz to 3.2 GHz, 345 fs jitter PLL with triple-modular redundant phase detector in 65 nm CMOS. Proceedings of the IEEE Asian Solid-State Circuits Conference (A-SSCC) 2016, Toyama, Japan.","DOI":"10.1109\/ASSCC.2016.7844191"},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"3432","DOI":"10.1109\/TNS.2006.886203","article-title":"A Hardened-by-Design Technique for RF Digital Phase-Locked Loops","volume":"53","author":"Loveless","year":"2006","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"1212","DOI":"10.1109\/TNS.2018.2826141","article-title":"A Compact, Low Jitter, CMOS 65 nm 4.8\u20136 GHz Phase-Locked Loop for Applications in HEP Experiments Front-End Electronics","volume":"65","author":"Mazza","year":"2018","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_16","doi-asserted-by":"crossref","unstructured":"Monda, D., Ciarpi, G., Mangraviti, G., Berti, L., and Saponara, S. (2020). Analysis and Comparison of Ring and LC-Tank Oscillators for 65 nm Integration of Rad-Hard VCO for SpaceFibre Applications, Lecture Notes in Electrical Engineering, Springer.","DOI":"10.1007\/978-3-030-37277-4_4"},{"key":"ref_17","doi-asserted-by":"crossref","unstructured":"Mestice, M., Neri, B., and Saponara, S. (2020). Analysis and Simulation of a PLL Architecture Towards a Fully Integrated 65 nm Solution for the New Spacefibre Standard, Lecture Notes in Electrical Engineering, Springer.","DOI":"10.1007\/978-3-030-37277-4_52"},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"1849","DOI":"10.1109\/TCOM.1980.1094619","article-title":"Charge-Pump Phase-Lock Loops","volume":"28","author":"Gardner","year":"1980","journal-title":"IEEE Trans. Commun."},{"key":"ref_19","unstructured":"Razavi, B. (2011). RF Microelectronics, Pearson Education. [2nd ed.]."},{"key":"ref_20","doi-asserted-by":"crossref","first-page":"241","DOI":"10.4313\/TEEM.2015.16.5.241","article-title":"High Performance CMOS Charge Pumps for Phase-locked Loop","volume":"16","author":"Rahman","year":"2015","journal-title":"Trans. Electr. Electron. Mater."},{"key":"ref_21","doi-asserted-by":"crossref","unstructured":"Zhang, C., Au, T., and Syrzycki, M. (2012, January 5\u20138). A high performance NMOS-switch high swing cascode charge pump for phase-locked loops. Proceedings of the IEEE 55th International MWSCAS, Boise, ID, USA.","DOI":"10.1109\/MWSCAS.2012.6292080"},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"2536","DOI":"10.1109\/TNS.2005.860718","article-title":"HBD layout isolation techniques for multiple node charge collection mitigation","volume":"52","author":"Black","year":"2005","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"2024","DOI":"10.1109\/TNS.1982.4336490","article-title":"Collection of Charge on Junction Nodes from Ion Tracks","volume":"29","author":"Messenger","year":"1982","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"829","DOI":"10.1109\/TCSI.2019.2954755","article-title":"Design, Implementation, and Experimental Verification of 5 Gbps, 800 Mrad TID and SEU-Tolerant Optical Modulators Drivers","volume":"67","author":"Ciarpi","year":"2020","journal-title":"IEEE Trans. Circuits Syst. I"},{"key":"ref_25","doi-asserted-by":"crossref","unstructured":"Ghosh, P.P., and Xiao, E. (2009, January 18\u201320). A 2.5 GHz radiation hard fully self-biased PLL using 0.25 \u00b5m SOS-CMOS technology. Proceedings of the IEEE International Conference on IC Design and Technology 2009, Austin, TX, USA.","DOI":"10.1109\/ICICDT.2009.5166278"},{"key":"ref_26","doi-asserted-by":"crossref","unstructured":"Herzel, F., Osmany, S.A., Schmalz, K., Winkler, W., Scheytt, J.C., Podrebersek, T., Follmann, R., and Heyer, H.V. (2009, January 7\u20139). An Integrated 18 GHz fractional-N PLL in SiGe BiCMOS technology for satellite communications. Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium 2009, Boston, MA, USA.","DOI":"10.1109\/RFIC.2009.5135551"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/20\/14\/4013\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T09:49:47Z","timestamp":1760176187000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/20\/14\/4013"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,7,19]]},"references-count":26,"journal-issue":{"issue":"14","published-online":{"date-parts":[[2020,7]]}},"alternative-id":["s20144013"],"URL":"https:\/\/doi.org\/10.3390\/s20144013","relation":{},"ISSN":["1424-8220"],"issn-type":[{"type":"electronic","value":"1424-8220"}],"subject":[],"published":{"date-parts":[[2020,7,19]]}}}