{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,18]],"date-time":"2026-06-18T16:13:24Z","timestamp":1781799204367,"version":"3.54.5"},"reference-count":43,"publisher":"MDPI AG","issue":"1","license":[{"start":{"date-parts":[[2021,1,5]],"date-time":"2021-01-05T00:00:00Z","timestamp":1609804800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/"}],"funder":[{"name":"ACHIEVE-ITN","award":["765866"],"award-info":[{"award-number":["765866"]}]},{"name":"Spanish MINECO and European Region Development Fund (ERDF\/FEDER)","award":["RTI2018-097088-B-C31"],"award-info":[{"award-number":["RTI2018-097088-B-C31"]}]},{"name":"US Office of Naval Research","award":["N00014-19-1-2156"],"award-info":[{"award-number":["N00014-19-1-2156"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Sensors"],"abstract":"<jats:p>In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [\u22120.953, 1.185] LSB, and an integral non-linearity (INL) within [\u22122.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.<\/jats:p>","DOI":"10.3390\/s21010308","type":"journal-article","created":{"date-parts":[[2021,1,5]],"date-time":"2021-01-05T10:35:12Z","timestamp":1609842912000},"page":"308","update-policy":"https:\/\/doi.org\/10.3390\/mdpi_crossmark_policy","source":"Crossref","is-referenced-by-count":43,"title":["A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA"],"prefix":"10.3390","volume":"21","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4760-3437","authenticated-orcid":false,"given":"Mojtaba","family":"Parsakordasiabi","sequence":"first","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Am\u00e9rico Vespucio s\/n, Parque Cient\u00edfico y Tecnol\u00f3gico de La Cartuja, 41092 Seville, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ion","family":"Vornicu","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Am\u00e9rico Vespucio s\/n, Parque Cient\u00edfico y Tecnol\u00f3gico de La Cartuja, 41092 Seville, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"\u00c1ngel","family":"Rodr\u00edguez-V\u00e1zquez","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Am\u00e9rico Vespucio s\/n, Parque Cient\u00edfico y Tecnol\u00f3gico de La Cartuja, 41092 Seville, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4230-3988","authenticated-orcid":false,"given":"Ricardo","family":"Carmona-Gal\u00e1n","sequence":"additional","affiliation":[{"name":"Instituto de Microelectr\u00f3nica de Sevilla, IMSE-CNM (CSIC-Universidad de Sevilla), Avda. Am\u00e9rico Vespucio s\/n, Parque Cient\u00edfico y Tecnol\u00f3gico de La Cartuja, 41092 Seville, Spain"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"1968","published-online":{"date-parts":[[2021,1,5]]},"reference":[{"key":"ref_1","doi-asserted-by":"crossref","unstructured":"Burri, S., Bruschini, C., and Charbon, E. (2017). LinoSPAD: A Compact Linear SPAD Camera System with 64 FPGA-Based TDC Modules for Versatile 50 ps Resolution Time-Resolved Imaging. Instruments, 1.","DOI":"10.3390\/instruments1010006"},{"key":"ref_2","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1109\/TCSI.2006.888679","article-title":"A CMOS 3-D Imager Based on Single Photon Avalanche Diode","volume":"54","author":"Stoppa","year":"2007","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_3","doi-asserted-by":"crossref","first-page":"2821","DOI":"10.1109\/TCSI.2017.2706324","article-title":"Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors","volume":"64","author":"Vornicu","year":"2017","journal-title":"IEEE Trans. Circuits Syst. I Regul. Pap."},{"key":"ref_4","first-page":"77801H","article-title":"High frame-rate TCSPC-FLIM using a novel SPAD-based image sensor","volume":"7780","author":"Gersbach","year":"2010","journal-title":"SPIE-Intl. Soc. Optical Eng."},{"key":"ref_5","doi-asserted-by":"crossref","unstructured":"Veerappan, C., Richardson, J., Walker, R., Li, D.D.-U., Fishburn, M.W., Maruyama, Y., Stoppa, D., Borghetti, F., Gersbach, M., and Henderson, R.K. (2011, January 20\u201324). A 160 \u00d7 128 single-photon image sensor with on-pixel 55ps 10b time-to-digital converter. Proceedings of the 2011 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA.","DOI":"10.1109\/ISSCC.2011.5746333"},{"key":"ref_6","doi-asserted-by":"crossref","first-page":"10484","DOI":"10.3390\/s101110484","article-title":"Photo-detectors for time of flight positron emission tomography (ToF-PET)","volume":"10","author":"Spanoudaki","year":"2010","journal-title":"Sensors"},{"key":"ref_7","doi-asserted-by":"crossref","first-page":"301","DOI":"10.1109\/JSSC.2013.2284351","article-title":"A Fully Digital 8\u00d716 SiPM Array for PET Applications With Per-Pixel TDCs and Real-Time Energy Output","volume":"49","author":"Braga","year":"2013","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref_8","first-page":"641","article-title":"Review of single-stage time-interval measurement modules implemented in FPGA devices","volume":"16","author":"Kowalski","year":"2009","journal-title":"Metrol. Meas. Syst."},{"key":"ref_9","doi-asserted-by":"crossref","first-page":"4205","DOI":"10.1109\/TIM.2019.2938436","article-title":"Recent Developments and Challenges in FPGA-Based Time-to-Digital Converters","volume":"68","author":"Machado","year":"2019","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"ref_10","doi-asserted-by":"crossref","unstructured":"Parsakordasiabi, M., Vornicu, I., Carmona-Gal\u00e1n, R., and Rodr\u00edguez-V\u00e1zquez, \u00c1. (2019, January 9\u201311). A survey on FPGA-based high-resolution TDCs. Proceedings of the 13th International Conference on Distributed Smart Cameras, Trento, Italy.","DOI":"10.1145\/3349801.3357129"},{"key":"ref_11","doi-asserted-by":"crossref","first-page":"236","DOI":"10.1109\/TNS.2006.869820","article-title":"A high-resolution time-to-digital converter implemented in field-programmable-gate-arrays","volume":"53","author":"Song","year":"2006","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_12","doi-asserted-by":"crossref","unstructured":"Favi, C., and Charbon, E. (2009, January 22\u201324). A 17ps time-to-digital converter implemented in 65nm FPGA technology. Proceedings of the ACM\/SIGDA international symposium on Field programmable gate arrays\u2014FPGA \u201909, Monterey, CA, USA.","DOI":"10.1145\/1508128.1508145"},{"key":"ref_13","doi-asserted-by":"crossref","first-page":"2203","DOI":"10.1109\/TNS.2013.2241789","article-title":"A 19.6 ps, FPGA-Based TDC With Multiple Channels for Open Source Applications","volume":"60","author":"Fishburn","year":"2013","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_14","doi-asserted-by":"crossref","first-page":"879","DOI":"10.1109\/19.863942","article-title":"Interpolating time counter with 100 ps resolution on a single FPGA device","volume":"49","author":"Szplet","year":"2000","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"ref_15","doi-asserted-by":"crossref","first-page":"530","DOI":"10.1109\/TIM.2008.2005080","article-title":"A Multihit Time-to-Digital Converter Architecture on FPGA","volume":"58","author":"Amiri","year":"2008","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"ref_16","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1016\/j.nima.2013.12.033","article-title":"The characterization and application of a low resource FPGA-based time to digital converter","volume":"739","author":"Balla","year":"2014","journal-title":"Nucl. Instrum. Methods Phys. Res. Sect. A Accel. Spectrometers Detect. Assoc. Equip."},{"key":"ref_17","first-page":"C03008","article-title":"A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module","volume":"7","author":"Fischer","year":"2012","journal-title":"J. Instrum."},{"key":"ref_18","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1016\/j.nima.2014.10.040","article-title":"A new delay line loops shrinking time-to-digital converter in low-cost FPGA","volume":"771","author":"Zhang","year":"2015","journal-title":"Nucl. Instrum. Methods Phys."},{"key":"ref_19","doi-asserted-by":"crossref","unstructured":"Zhang, M., Wang, H., and Liu, Y. (2017). A 7.4 ps FPGA-Based TDC with a 1024-Unit Measurement Matrix. Sensors, 17.","DOI":"10.3390\/s17040865"},{"key":"ref_20","doi-asserted-by":"crossref","unstructured":"Wu, J., and Shi, Z. (2008, January 19\u201325). The 10-ps wave union TDC: Improving FPGA TDC resolution beyond its cell delay. Proceedings of the 2008 IEEE Nuclear Science Symposium Conference Record, Dresden, Germany.","DOI":"10.1109\/NSSMIC.2008.4775079"},{"key":"ref_21","doi-asserted-by":"crossref","first-page":"773","DOI":"10.1109\/TNS.2015.2421319","article-title":"A 128-Channel, 710 M Samples\/Second, and Less Than 10 ps RMS Resolution Time-to-Digital Converter Implemented in a Kintex-7 FPGA","volume":"62","author":"Liu","year":"2015","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_22","doi-asserted-by":"crossref","first-page":"231","DOI":"10.1109\/TBCAS.2015.2389227","article-title":"Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA","volume":"10","author":"Won","year":"2016","journal-title":"IEEE Trans. Biomed. Circuits Syst."},{"key":"ref_23","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1016\/j.nima.2018.02.064","article-title":"Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA","volume":"891","author":"Kuang","year":"2018","journal-title":"Nucl. Instrum. Methods Phys. Res. Sect. A Accel. Spectrometers Detect. Assoc. Equip."},{"key":"ref_24","doi-asserted-by":"crossref","first-page":"1678","DOI":"10.1109\/TIM.2016.2534670","article-title":"Time-to-Digital Converter Using a Tuned-Delay Line Evaluated in 28-, 40-, and 45-nm FPGAs","volume":"65","author":"Won","year":"2016","journal-title":"IEEE Trans. Instrum. Meas."},{"key":"ref_25","doi-asserted-by":"crossref","first-page":"1543","DOI":"10.1109\/TNS.2010.2045901","article-title":"Several Key Issues on Implementing Delay Line Based TDCs Using FPGAs","volume":"57","author":"Wu","year":"2010","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_26","doi-asserted-by":"crossref","first-page":"2617","DOI":"10.1109\/TNS.2016.2596305","article-title":"A 3.9 ps Time-Interval RMS Precision Time-to-Digital Converter Using a Dual-Sampling Method in an UltraScale FPGA","volume":"63","author":"Wang","year":"2016","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_27","doi-asserted-by":"crossref","first-page":"3544","DOI":"10.1109\/TNS.2013.2265555","article-title":"A stepped-up tree encoder for the 10-ps wave union TDC","volume":"60","author":"Hu","year":"2013","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_28","doi-asserted-by":"crossref","first-page":"2003","DOI":"10.1109\/TNS.2015.2475630","article-title":"A Nonlinearity Minimization-Oriented Resource-Saving Time-to-Digital Converter Implemented in a 28 nm Xilinx FPGA","volume":"62","author":"Wang","year":"2015","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_29","doi-asserted-by":"crossref","first-page":"3265","DOI":"10.1109\/TIE.2018.2842787","article-title":"Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs","volume":"66","author":"Chen","year":"2019","journal-title":"IEEE Trans. Ind. Electron."},{"key":"ref_30","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/TNS.2017.2746626","article-title":"A 3.9 ps RMS Precision Time-to-Digital Converter Using Ones Counter Encoding Scheme in a Kintex-7 FPGA","volume":"64","author":"Wang","year":"2017","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_31","unstructured":"Wu, J., Shi, Z., and Wang, I. (2003, January 19\u201325). Firmware-only implementation of time-to-digital converter (TDC) in field-programmable gate array (FPGA). Proceedings of the 2003 IEEE Nuclear Science Symposium. Conference Record (IEEE Cat. No.03CH37515), Portland, OR, USA."},{"key":"ref_32","doi-asserted-by":"crossref","first-page":"446","DOI":"10.1109\/TNS.2009.2037958","article-title":"A fully fledged TDC implemented in field-programmable gate arrays","volume":"57","author":"Wang","year":"2010","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_33","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1016\/0029-554X(70)90095-9","article-title":"Differential linearity testing and precision calibration of multichannel time sorters","volume":"77","author":"Cova","year":"2002","journal-title":"Nucl. Instrum. Methods"},{"key":"ref_34","doi-asserted-by":"crossref","unstructured":"Arabul, E., Girach, A., Rarity, J., and Dahnoun, N. (2017, January 18\u201320). Precise multi-channel timing analysis system for multi-stop LIDAR correlation. Proceedings of the 2017 IEEE International Conference on Imaging Systems and Techniques (IST), Beijing, China.","DOI":"10.1109\/IST.2017.8261560"},{"key":"ref_35","doi-asserted-by":"crossref","first-page":"054707","DOI":"10.1063\/1.5008610","article-title":"An 18-ps TDC using timing adjustment and bin realignment methods in a Cyclone-IV FPGA","volume":"89","author":"Cao","year":"2018","journal-title":"Rev. Sci. Instrum."},{"key":"ref_36","doi-asserted-by":"crossref","first-page":"094","DOI":"10.22323\/1.370.0094","article-title":"Highly-linear FPGA-based Data Acquisition System for Multi-channel SiPM Readout","volume":"Volume 370","author":"Townsend","year":"2020","journal-title":"Proceedings of the Topical Workshop on Electronics for Particle Physics\u2014PoS(TWEPP2019)"},{"key":"ref_37","unstructured":"Homulle, H., and Charbon, E. (2021, January 04). Basic FPGA TDC Design. Available online: http:\/\/cas.tudelft.nl\/fpga_tdc\/TDC_basic.html."},{"key":"ref_38","doi-asserted-by":"crossref","first-page":"680","DOI":"10.1109\/TNS.2018.2790703","article-title":"Design and characterization of a low-cost FPGA-based TDC","volume":"65","author":"Tontini","year":"2018","journal-title":"IEEE Trans. Nucl. Sci."},{"key":"ref_39","unstructured":"Kelly, O. (2021, January 04). XEM7310 User\u2019s Manual. Available online: https:\/\/docs.opalkelly.com\/display\/XEM7310."},{"key":"ref_40","unstructured":"Kelly, O. (2021, January 04). Front Panel User\u2019s Manual. Available online: http:\/\/assets00.opalkelly.com\/library\/FrontPanel-UM.pdf."},{"key":"ref_41","unstructured":"Xilinx (2021, January 04). Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181). 18 June 2018. Available online: https:\/\/www.xilinx.com\/support\/documentation\/data_sheets\/ds181_Artix_7_Data_Sheet.pdf."},{"key":"ref_42","unstructured":"Xilinx (2021, January 04). 7 Series FPGAs Clocking Resources (UG472). 30 July 2018. Available online: https:\/\/www.xilinx.com\/support\/documentation\/user_guides\/ug472_7Series_Clocking.pdf."},{"key":"ref_43","doi-asserted-by":"crossref","first-page":"1009","DOI":"10.1109\/JSSC.2013.2237996","article-title":"A 7 bit, 3.75 ps Resolution Two-Step Time-to-Digital Converter in 65 nm CMOS Using Pulse-Train Time Amplifier","volume":"48","author":"Kim","year":"2013","journal-title":"IEEE J. Solid-State Circuits"}],"container-title":["Sensors"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/www.mdpi.com\/1424-8220\/21\/1\/308\/pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,11]],"date-time":"2025-10-11T05:07:06Z","timestamp":1760159226000},"score":1,"resource":{"primary":{"URL":"https:\/\/www.mdpi.com\/1424-8220\/21\/1\/308"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,1,5]]},"references-count":43,"journal-issue":{"issue":"1","published-online":{"date-parts":[[2021,1]]}},"alternative-id":["s21010308"],"URL":"https:\/\/doi.org\/10.3390\/s21010308","relation":{},"ISSN":["1424-8220"],"issn-type":[{"value":"1424-8220","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,1,5]]}}}